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[X86] Simplify some code a little by removing a dulicate variable and combinining two if statements. NFCI

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llvm-svn: 287443
This commit is contained in:
Craig Topper 2016-11-19 17:33:17 +00:00
parent 206a49e5a7
commit 5b8b954f1c
1 changed files with 15 additions and 17 deletions
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32
lib/Target/X86/X86ISelLowering.cpp
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@ -27738,6 +27738,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
SDValue LHS = N->getOperand(1); SDValue LHS = N->getOperand(1);
SDValue RHS = N->getOperand(2); SDValue RHS = N->getOperand(2);
EVT VT = LHS.getValueType(); EVT VT = LHS.getValueType();
EVT CondVT = Cond.getValueType();
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); const TargetLowering &TLI = DAG.getTargetLoweringInfo();
// If we have SSE[12] support, try to form min/max nodes. SSE min/max // If we have SSE[12] support, try to form min/max nodes. SSE min/max
@ -27886,23 +27887,20 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
} }
EVT CondVT = Cond.getValueType(); // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
if (Subtarget.hasAVX512() && VT.isVector() && CondVT.isVector() && // lowering on KNL. In this case we convert it to
CondVT.getVectorElementType() == MVT::i1) { // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
// v16i8 (select v16i1, v16i8, v16i8) does not have a proper // The same situation for all 128 and 256-bit vectors of i8 and i16.
// lowering on KNL. In this case we convert it to // Since SKX these selects have a proper lowering.
// v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction. if (Subtarget.hasAVX512() && CondVT.isVector() &&
// The same situation for all 128 and 256-bit vectors of i8 and i16. CondVT.getVectorElementType() == MVT::i1 &&
// Since SKX these selects have a proper lowering. (VT.is128BitVector() || VT.is256BitVector()) &&
EVT OpVT = LHS.getValueType(); (VT.getVectorElementType() == MVT::i8 ||
if ((OpVT.is128BitVector() || OpVT.is256BitVector()) && VT.getVectorElementType() == MVT::i16) &&
(OpVT.getVectorElementType() == MVT::i8 || !(Subtarget.hasBWI() && Subtarget.hasVLX())) {
OpVT.getVectorElementType() == MVT::i16) && Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Cond);
!(Subtarget.hasBWI() && Subtarget.hasVLX())) { DCI.AddToWorklist(Cond.getNode());
Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond); return DAG.getNode(N->getOpcode(), DL, VT, Cond, LHS, RHS);
DCI.AddToWorklist(Cond.getNode());
return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
}
} }
if (SDValue V = combineSelectOfTwoConstants(N, DAG)) if (SDValue V = combineSelectOfTwoConstants(N, DAG))