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AMDGPU/R600: Move intrinsics to IntrinsicsAMDGPU.td

Browse Source 
Reviewers: arsenm, nhaehnle, jvesely

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D47487

llvm-svn: 333720
This commit is contained in:
Tom Stellard 2018-06-01 02:19:46 +00:00
parent 108eb5a52b
commit 5c29ac423b
4 changed files with 55 additions and 70 deletions
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49
include/llvm/IR/IntrinsicsAMDGPU.td
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@ -80,6 +80,55 @@ def int_r600_store_stream_output : Intrinsic<
[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []
>;
class TextureIntrinsicFloatInput : Intrinsic<[llvm_v4f32_ty], [
llvm_v4f32_ty, // Coord
llvm_i32_ty, // offset_x
llvm_i32_ty, // offset_y,
llvm_i32_ty, // offset_z,
llvm_i32_ty, // resource_id
llvm_i32_ty, // samplerid
llvm_i32_ty, // coord_type_x
llvm_i32_ty, // coord_type_y
llvm_i32_ty, // coord_type_z
llvm_i32_ty], // coord_type_w
[IntrNoMem]
>;
class TextureIntrinsicInt32Input : Intrinsic<[llvm_v4i32_ty], [
llvm_v4i32_ty, // Coord
llvm_i32_ty, // offset_x
llvm_i32_ty, // offset_y,
llvm_i32_ty, // offset_z,
llvm_i32_ty, // resource_id
llvm_i32_ty, // samplerid
llvm_i32_ty, // coord_type_x
llvm_i32_ty, // coord_type_y
llvm_i32_ty, // coord_type_z
llvm_i32_ty], // coord_type_w
[IntrNoMem]
>;
def int_r600_store_swizzle :
Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []
>;
def int_r600_tex : TextureIntrinsicFloatInput;
def int_r600_texc : TextureIntrinsicFloatInput;
def int_r600_txl : TextureIntrinsicFloatInput;
def int_r600_txlc : TextureIntrinsicFloatInput;
def int_r600_txb : TextureIntrinsicFloatInput;
def int_r600_txbc : TextureIntrinsicFloatInput;
def int_r600_txf : TextureIntrinsicInt32Input;
def int_r600_txq : TextureIntrinsicInt32Input;
def int_r600_ddx : TextureIntrinsicFloatInput;
def int_r600_ddy : TextureIntrinsicFloatInput;
def int_r600_dot4 : Intrinsic<[llvm_float_ty],
[llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem, IntrSpeculatable]
>;
def int_r600_kill : Intrinsic<[], [llvm_float_ty], []>;
} // End TargetPrefix = "r600"
let TargetPrefix = "amdgcn" in {

12
lib/Target/AMDGPU/R600ISelLowering.cpp
View File

@ -472,7 +472,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
unsigned IntrinsicID =
cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
switch (IntrinsicID) {
case AMDGPUIntrinsic::r600_store_swizzle: {
case Intrinsic::r600_store_swizzle: {
SDLoc DL(Op);
const SDValue Args[8] = {
Chain,
@ -499,14 +499,14 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
EVT VT = Op.getValueType();
SDLoc DL(Op);
switch (IntrinsicID) {
case AMDGPUIntrinsic::r600_tex:
case AMDGPUIntrinsic::r600_texc: {
case Intrinsic::r600_tex:
case Intrinsic::r600_texc: {
unsigned TextureOp;
switch (IntrinsicID) {
case AMDGPUIntrinsic::r600_tex:
case Intrinsic::r600_tex:
TextureOp = 0;
break;
case AMDGPUIntrinsic::r600_texc:
case Intrinsic::r600_texc:
TextureOp = 1;
break;
default:
@ -536,7 +536,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
};
return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
}
case AMDGPUIntrinsic::r600_dot4: {
case Intrinsic::r600_dot4: {
SDValue Args[8] = {
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
DAG.getConstant(0, DL, MVT::i32)),

1
lib/Target/AMDGPU/R600Instructions.td
View File

@ -12,7 +12,6 @@
//
//===----------------------------------------------------------------------===//
include "R600Intrinsics.td"
include "R600InstrFormats.td"
// FIXME: Should not be arbitrarily split from other R600 inst classes.

63
lib/Target/AMDGPU/R600Intrinsics.td
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@ -1,63 +0,0 @@
//===-- R600Intrinsics.td - R600 Instrinsic defs -------*- tablegen -*-----===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// R600 Intrinsic Definitions
//
//===----------------------------------------------------------------------===//
class TextureIntrinsicFloatInput : Intrinsic<[llvm_v4f32_ty], [
llvm_v4f32_ty, // Coord
llvm_i32_ty, // offset_x
llvm_i32_ty, // offset_y,
llvm_i32_ty, // offset_z,
llvm_i32_ty, // resource_id
llvm_i32_ty, // samplerid
llvm_i32_ty, // coord_type_x
llvm_i32_ty, // coord_type_y
llvm_i32_ty, // coord_type_z
llvm_i32_ty], // coord_type_w
[IntrNoMem]
>;
class TextureIntrinsicInt32Input : Intrinsic<[llvm_v4i32_ty], [
llvm_v4i32_ty, // Coord
llvm_i32_ty, // offset_x
llvm_i32_ty, // offset_y,
llvm_i32_ty, // offset_z,
llvm_i32_ty, // resource_id
llvm_i32_ty, // samplerid
llvm_i32_ty, // coord_type_x
llvm_i32_ty, // coord_type_y
llvm_i32_ty, // coord_type_z
llvm_i32_ty], // coord_type_w
[IntrNoMem]
>;
let TargetPrefix = "r600", isTarget = 1 in {
def int_r600_store_swizzle :
Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []
>;
def int_r600_tex : TextureIntrinsicFloatInput;
def int_r600_texc : TextureIntrinsicFloatInput;
def int_r600_txl : TextureIntrinsicFloatInput;
def int_r600_txlc : TextureIntrinsicFloatInput;
def int_r600_txb : TextureIntrinsicFloatInput;
def int_r600_txbc : TextureIntrinsicFloatInput;
def int_r600_txf : TextureIntrinsicInt32Input;
def int_r600_txq : TextureIntrinsicInt32Input;
def int_r600_ddx : TextureIntrinsicFloatInput;
def int_r600_ddy : TextureIntrinsicFloatInput;
def int_r600_dot4 : Intrinsic<[llvm_float_ty],
[llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem, IntrSpeculatable]
>;
} // End TargetPrefix = "r600", isTarget = 1