mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-27 06:54:30 +00:00
Reviewed at reviews.llvm.org/D17133
llvm-svn: 262005
This commit is contained in:
Chris Dewhurst
parent
a25189ea0f
commit
5c895f8b77
@ -150,6 +150,22 @@ public:
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Sparc::L0_L1, Sparc::L2_L3, Sparc::L4_L5, Sparc::L6_L7,
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Sparc::I0_I1, Sparc::I2_I3, Sparc::I4_I5, Sparc::I6_I7};
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static const MCPhysReg CoprocRegs[32] = {
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Sparc::C0, Sparc::C1, Sparc::C2, Sparc::C3,
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Sparc::C4, Sparc::C5, Sparc::C6, Sparc::C7,
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Sparc::C8, Sparc::C9, Sparc::C10, Sparc::C11,
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Sparc::C12, Sparc::C13, Sparc::C14, Sparc::C15,
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Sparc::C16, Sparc::C17, Sparc::C18, Sparc::C19,
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Sparc::C20, Sparc::C21, Sparc::C22, Sparc::C23,
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Sparc::C24, Sparc::C25, Sparc::C26, Sparc::C27,
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Sparc::C28, Sparc::C29, Sparc::C30, Sparc::C31 };
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static const MCPhysReg CoprocPairRegs[] = {
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Sparc::C0_C1, Sparc::C2_C3, Sparc::C4_C5, Sparc::C6_C7,
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Sparc::C8_C9, Sparc::C10_C11, Sparc::C12_C13, Sparc::C14_C15,
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Sparc::C16_C17, Sparc::C18_C19, Sparc::C20_C21, Sparc::C22_C23,
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Sparc::C24_C25, Sparc::C26_C27, Sparc::C28_C29, Sparc::C30_C31};
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/// SparcOperand - Instances of this class represent a parsed Sparc machine
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/// instruction.
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class SparcOperand : public MCParsedAsmOperand {
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@ -161,6 +177,8 @@ public:
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rk_FloatReg,
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rk_DoubleReg,
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rk_QuadReg,
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rk_CoprocReg,
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rk_CoprocPairReg,
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rk_Special,
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};
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@ -224,6 +242,9 @@ public:
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|| Reg.Kind == rk_DoubleReg));
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}
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bool isCoprocReg() const {
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return (Kind == k_Register && Reg.Kind == rk_CoprocReg);
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}
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StringRef getToken() const {
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assert(Kind == k_Token && "Invalid access!");
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@ -398,6 +419,19 @@ public:
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return true;
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}
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static bool MorphToCoprocPairReg(SparcOperand &Op) {
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unsigned Reg = Op.getReg();
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assert(Op.Reg.Kind == rk_CoprocReg);
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unsigned regIdx = 32;
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if (Reg >= Sparc::C0 && Reg <= Sparc::C31)
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regIdx = Reg - Sparc::C0;
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if (regIdx % 2 || regIdx > 31)
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return false;
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Op.Reg.RegNum = CoprocPairRegs[regIdx / 2];
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Op.Reg.Kind = rk_CoprocPairReg;
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return true;
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}
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static std::unique_ptr<SparcOperand>
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MorphToMEMrr(unsigned Base, std::unique_ptr<SparcOperand> Op) {
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unsigned offsetReg = Op->getReg();
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@ -809,6 +843,15 @@ SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
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case Sparc::FSR:
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Op = SparcOperand::CreateToken("%fsr", S);
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break;
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case Sparc::FQ:
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Op = SparcOperand::CreateToken("%fq", S);
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break;
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case Sparc::CPSR:
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Op = SparcOperand::CreateToken("%csr", S);
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break;
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case Sparc::CPQ:
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Op = SparcOperand::CreateToken("%cq", S);
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break;
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case Sparc::WIM:
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Op = SparcOperand::CreateToken("%wim", S);
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break;
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@ -941,6 +984,24 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
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return true;
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}
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if (name.equals("fq")) {
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RegNo = Sparc::FQ;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("csr")) {
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RegNo = Sparc::CPSR;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("cq")) {
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RegNo = Sparc::CPQ;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("wim")) {
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RegNo = Sparc::WIM;
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RegKind = SparcOperand::rk_Special;
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@ -1025,6 +1086,15 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
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return true;
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}
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// %c0 - %c31
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if (name.substr(0, 1).equals_lower("c")
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&& !name.substr(1).getAsInteger(10, intVal)
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&& intVal < 32) {
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RegNo = CoprocRegs[intVal];
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RegKind = SparcOperand::rk_CoprocReg;
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return true;
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}
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if (name.equals("tpc")) {
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RegNo = Sparc::TPC;
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RegKind = SparcOperand::rk_Special;
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@ -1215,5 +1285,9 @@ unsigned SparcAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,
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if (SparcOperand::MorphToIntPairReg(Op))
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return MCTargetAsmParser::Match_Success;
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}
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if (Op.isCoprocReg() && Kind == MCK_CoprocPair) {
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if (SparcOperand::MorphToCoprocPairReg(Op))
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return MCTargetAsmParser::Match_Success;
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}
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return Match_InvalidOperand;
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}
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@ -130,6 +130,25 @@ static const uint16_t IntPairDecoderTable[] = {
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SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7,
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};
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static const unsigned CPRegDecoderTable[] = {
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SP::C0, SP::C1, SP::C2, SP::C3,
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SP::C4, SP::C5, SP::C6, SP::C7,
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SP::C8, SP::C9, SP::C10, SP::C11,
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SP::C12, SP::C13, SP::C14, SP::C15,
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SP::C16, SP::C17, SP::C18, SP::C19,
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SP::C20, SP::C21, SP::C22, SP::C23,
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SP::C24, SP::C25, SP::C26, SP::C27,
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SP::C28, SP::C29, SP::C30, SP::C31
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};
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static const uint16_t CPPairDecoderTable[] = {
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SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7,
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SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15,
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SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23,
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SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31
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};
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static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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@ -191,6 +210,17 @@ static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = CPRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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@ -233,6 +263,16 @@ static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo,
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return S;
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}
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static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned RegisterPair = CPPairDecoderTable[RegNo/2];
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Inst.addOperand(MCOperand::createReg(RegisterPair));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address,
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@ -243,6 +283,10 @@ static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
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@ -253,6 +297,10 @@ static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
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@ -390,6 +438,18 @@ static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
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DecodeQFPRegsRegisterClass);
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}
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static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, true,
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DecodeCPRegsRegisterClass);
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}
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static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, true,
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DecodeCPPairRegisterClass);
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}
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static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, false,
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@ -420,6 +480,18 @@ static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
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DecodeQFPRegsRegisterClass);
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}
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static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, false,
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DecodeCPRegsRegisterClass);
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}
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static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, false,
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DecodeCPPairRegisterClass);
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}
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static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
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uint64_t Address, uint64_t Offset,
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uint64_t Width, MCInst &MI,
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@ -235,12 +235,28 @@ def FCC_UL : FCC_VAL<19>; // Unordered or Less
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def FCC_LG : FCC_VAL<18>; // Less or Greater
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def FCC_NE : FCC_VAL<17>; // Not Equal
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def FCC_E : FCC_VAL<25>; // Equal
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def FCC_UE : FCC_VAL<24>; // Unordered or Equal
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def FCC_GE : FCC_VAL<25>; // Greater or Equal
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def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
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def FCC_LE : FCC_VAL<27>; // Less or Equal
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def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
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def FCC_O : FCC_VAL<29>; // Ordered
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def FCC_UE : FCC_VAL<26>; // Unordered or Equal
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def FCC_GE : FCC_VAL<27>; // Greater or Equal
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def FCC_UGE : FCC_VAL<28>; // Unordered or Greater or Equal
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def FCC_LE : FCC_VAL<29>; // Less or Equal
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def FCC_ULE : FCC_VAL<30>; // Unordered or Less or Equal
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def FCC_O : FCC_VAL<31>; // Ordered
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class CPCC_VAL<int N> : PatLeaf<(i32 N)>;
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def CPCC_3 : CPCC_VAL<39>; // 3
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def CPCC_2 : CPCC_VAL<38>; // 2
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def CPCC_23 : CPCC_VAL<37>; // 2 or 3
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def CPCC_1 : CPCC_VAL<36>; // 1
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def CPCC_13 : CPCC_VAL<35>; // 1 or 3
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def CPCC_12 : CPCC_VAL<34>; // 1 or 2
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def CPCC_123 : CPCC_VAL<33>; // 1 or 2 or 3
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def CPCC_0 : CPCC_VAL<41>; // 0
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def CPCC_03 : CPCC_VAL<42>; // 0 or 3
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def CPCC_02 : CPCC_VAL<43>; // 0 or 2
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def CPCC_023 : CPCC_VAL<44>; // 0 or 2 or 3
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def CPCC_01 : CPCC_VAL<45>; // 0 or 1
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def CPCC_013 : CPCC_VAL<46>; // 0 or 1 or 3
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def CPCC_012 : CPCC_VAL<47>; // 0 or 1 or 2
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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@ -445,6 +461,20 @@ let DecoderMethod = "DecodeLoadQFP" in
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defm LDQF : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,
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Requires<[HasV9, HasHardQuad]>;
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let DecoderMethod = "DecodeLoadCP" in
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defm LDC : Load<"ld", 0b110000, load, CoprocRegs, i32>;
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let DecoderMethod = "DecodeLoadCPPair" in
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defm LDDC : Load<"ldd", 0b110011, load, CoprocPair, v2i32>;
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let DecoderMethod = "DecodeLoadCP", Defs = [CPSR] in {
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let rd = 0 in {
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def LDCSRrr : F3_1<3, 0b110001, (outs), (ins MEMrr:$addr),
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"ld [$addr], %csr", []>;
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def LDCSRri : F3_2<3, 0b110001, (outs), (ins MEMri:$addr),
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"ld [$addr], %csr", []>;
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}
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}
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let DecoderMethod = "DecodeLoadFP" in
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let Defs = [FSR] in {
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let rd = 0 in {
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@ -486,6 +516,27 @@ let DecoderMethod = "DecodeStoreQFP" in
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defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,
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Requires<[HasV9, HasHardQuad]>;
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let DecoderMethod = "DecodeStoreCP" in
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defm STC : Store<"st", 0b110100, store, CoprocRegs, i32>;
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let DecoderMethod = "DecodeStoreCPPair" in
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defm STDC : Store<"std", 0b110111, store, CoprocPair, v2i32>;
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let DecoderMethod = "DecodeStoreCP", rd = 0 in {
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let Defs = [CPSR] in {
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def STCSRrr : F3_1<3, 0b110101, (outs MEMrr:$addr), (ins),
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"st %csr, [$addr]", []>;
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def STCSRri : F3_2<3, 0b110101, (outs MEMri:$addr), (ins),
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"st %csr, [$addr]", []>;
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}
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let Defs = [CPQ] in {
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def STDCQrr : F3_1<3, 0b110110, (outs MEMrr:$addr), (ins),
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"std %cq, [$addr]", []>;
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def STDCQri : F3_2<3, 0b110110, (outs MEMri:$addr), (ins),
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"std %cq, [$addr]", []>;
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}
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}
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let DecoderMethod = "DecodeStoreFP" in
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let Defs = [FSR] in {
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let rd = 0 in {
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@ -501,6 +552,14 @@ let DecoderMethod = "DecodeStoreFP" in
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"stx %fsr, [$addr]", []>, Requires<[HasV9]>;
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}
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}
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let Defs = [FQ] in {
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let rd = 0 in {
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def STDFQrr : F3_1<3, 0b100110, (outs MEMrr:$addr), (ins),
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"std %fq, [$addr]", []>;
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def STDFQri : F3_2<3, 0b100110, (outs MEMri:$addr), (ins),
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"std %fq, [$addr]", []>;
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}
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}
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// Section B.8 - SWAP Register with Memory Instruction
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// (Atomic swap)
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@ -755,7 +814,25 @@ let Uses = [FCC0] in {
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let Predicates = [HasV9] in
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defm BPF : FPredBranch;
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// Section B.22 - Branch on Co-processor Condition Codes Instructions, p. 123
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let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
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// co-processor conditional branch class:
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class CPBranchSP<dag ins, string asmstr, list<dag> pattern>
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: F2_2<0b111, 0, (outs), ins, asmstr, pattern>;
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// co-processor conditional branch with annul class:
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class CPBranchSPA<dag ins, string asmstr, list<dag> pattern>
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: F2_2<0b111, 1, (outs), ins, asmstr, pattern>;
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} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
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def CBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
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"cb$cond $imm22",
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[(SPbrfcc bb:$imm22, imm:$cond)]>;
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def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
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"cb$cond,a $imm22", []>;
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// Section B.24 - Call and Link Instruction, p. 125
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// This is the only Format 1 instruction
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let Uses = [O6],
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@ -62,6 +62,12 @@ foreach I = 0-3 in
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def FSR : SparcCtrlReg<0, "FSR">; // Floating-point state register.
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def FQ : SparcCtrlReg<0, "FQ">; // Floating-point deferred-trap queue.
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def CPSR : SparcCtrlReg<0, "CPSR">; // Co-processor state register.
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def CPQ : SparcCtrlReg<0, "CPQ">; // Co-processor queue.
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// Y register
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def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;
|
||||
// Ancillary state registers (implementation defined)
|
||||
@ -204,6 +210,40 @@ def D13 : Rd<26, "F26", [F26, F27]>, DwarfRegNum<[85]>;
|
||||
def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<[86]>;
|
||||
def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[87]>;
|
||||
|
||||
// Co-processor registers
|
||||
def C0 : Ri< 0, "C0">;
|
||||
def C1 : Ri< 1, "C1">;
|
||||
def C2 : Ri< 2, "C2">;
|
||||
def C3 : Ri< 3, "C3">;
|
||||
def C4 : Ri< 4, "C4">;
|
||||
def C5 : Ri< 5, "C5">;
|
||||
def C6 : Ri< 6, "C6">;
|
||||
def C7 : Ri< 7, "C7">;
|
||||
def C8 : Ri< 8, "C8">;
|
||||
def C9 : Ri< 9, "C9">;
|
||||
def C10 : Ri< 10, "C10">;
|
||||
def C11 : Ri< 11, "C11">;
|
||||
def C12 : Ri< 12, "C12">;
|
||||
def C13 : Ri< 13, "C13">;
|
||||
def C14 : Ri< 14, "C14">;
|
||||
def C15 : Ri< 15, "C15">;
|
||||
def C16 : Ri< 16, "C16">;
|
||||
def C17 : Ri< 17, "C17">;
|
||||
def C18 : Ri< 18, "C18">;
|
||||
def C19 : Ri< 19, "C19">;
|
||||
def C20 : Ri< 20, "C20">;
|
||||
def C21 : Ri< 21, "C21">;
|
||||
def C22 : Ri< 22, "C22">;
|
||||
def C23 : Ri< 23, "C23">;
|
||||
def C24 : Ri< 24, "C24">;
|
||||
def C25 : Ri< 25, "C25">;
|
||||
def C26 : Ri< 26, "C26">;
|
||||
def C27 : Ri< 27, "C27">;
|
||||
def C28 : Ri< 28, "C28">;
|
||||
def C29 : Ri< 29, "C29">;
|
||||
def C30 : Ri< 30, "C30">;
|
||||
def C31 : Ri< 31, "C31">;
|
||||
|
||||
// Unaliased double precision floating point registers.
|
||||
// FIXME: Define DwarfRegNum for these registers.
|
||||
def D16 : SparcReg< 1, "F32">;
|
||||
@ -259,6 +299,24 @@ def I2_I3 : Rdi<26, "I2", [I2, I3]>;
|
||||
def I4_I5 : Rdi<28, "I4", [I4, I5]>;
|
||||
def I6_I7 : Rdi<30, "I6", [I6, I7]>;
|
||||
|
||||
// Aliases of the co-processor registers used for LDD/STD double-word operations
|
||||
def C0_C1 : Rdi<0, "C0", [C0, C1]>;
|
||||
def C2_C3 : Rdi<2, "C2", [C2, C3]>;
|
||||
def C4_C5 : Rdi<4, "C4", [C4, C5]>;
|
||||
def C6_C7 : Rdi<6, "C6", [C6, C7]>;
|
||||
def C8_C9 : Rdi<8, "C8", [C8, C9]>;
|
||||
def C10_C11 : Rdi<10, "C10", [C10, C11]>;
|
||||
def C12_C13 : Rdi<12, "C12", [C12, C13]>;
|
||||
def C14_C15 : Rdi<14, "C14", [C14, C15]>;
|
||||
def C16_C17 : Rdi<16, "C16", [C16, C17]>;
|
||||
def C18_C19 : Rdi<18, "C18", [C18, C19]>;
|
||||
def C20_C21 : Rdi<20, "C20", [C20, C21]>;
|
||||
def C22_C23 : Rdi<22, "C22", [C22, C23]>;
|
||||
def C24_C25 : Rdi<24, "C24", [C24, C25]>;
|
||||
def C26_C27 : Rdi<26, "C26", [C26, C27]>;
|
||||
def C28_C29 : Rdi<28, "C28", [C28, C29]>;
|
||||
def C30_C31 : Rdi<30, "C30", [C30, C31]>;
|
||||
|
||||
// Register classes.
|
||||
//
|
||||
// FIXME: the register order should be defined in terms of the preferred
|
||||
@ -273,6 +331,7 @@ def IntRegs : RegisterClass<"SP", [i32, i64], 32,
|
||||
(sequence "L%u", 0, 7),
|
||||
(sequence "O%u", 0, 7))>;
|
||||
|
||||
|
||||
// Should be in the same order as IntRegs.
|
||||
def IntPair : RegisterClass<"SP", [v2i32], 64,
|
||||
(add I0_I1, I2_I3, I4_I5, I6_I7,
|
||||
@ -296,10 +355,21 @@ def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>;
|
||||
// Floating point control register classes.
|
||||
def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>;
|
||||
|
||||
// Ancillary state registers
|
||||
def ASRRegs : RegisterClass<"SP", [i32], 32,
|
||||
(add Y, (sequence "ASR%u", 1, 31))> {
|
||||
let isAllocatable = 0;
|
||||
let isAllocatable = 0 in {
|
||||
// Ancillary state registers
|
||||
def ASRRegs : RegisterClass<"SP", [i32], 32,
|
||||
(add Y, (sequence "ASR%u", 1, 31))>;
|
||||
|
||||
// This register class should not be used to hold i64 values.
|
||||
def CoprocRegs : RegisterClass<"SP", [i32], 32,
|
||||
(add (sequence "C%u", 0, 31))>;
|
||||
|
||||
// Should be in the same order as CoprocRegs.
|
||||
def CoprocPair : RegisterClass<"SP", [v2i32], 64,
|
||||
(add C0_C1, C2_C3, C4_C5, C6_C7,
|
||||
C8_C9, C10_C11, C12_C13, C14_C15,
|
||||
C16_C17, C18_C19, C20_C21, C22_C23,
|
||||
C24_C25, C26_C27, C28_C29, C30_C31)>;
|
||||
}
|
||||
|
||||
// Privileged Registers
|
||||
|
||||
@ -32,3 +32,15 @@
|
||||
|
||||
# CHECK: wr %i0, 5, %tbr
|
||||
0x81 0x9e 0x20 0x05
|
||||
|
||||
# CHECK: st %fsr, [%i5]
|
||||
0xc1 0x2f 0x40 0x00
|
||||
|
||||
# CHECK: st %csr, [%i5]
|
||||
0xc1 0xaf 0x40 0x00
|
||||
|
||||
# CHECK: std %cq, [%o3+-93]
|
||||
0xc1 0xb2 0xff 0xa3
|
||||
|
||||
# CHECK: std %fq, [%i5+%l1]
|
||||
0xc1 0x37 0x40 0x11
|
||||
@ -65,8 +65,8 @@
|
||||
faddq %f0, %f4, %f8
|
||||
|
||||
! make sure we can handle V9 double registers and their aliased quad registers.
|
||||
! CHECK: faddd %f32, %f34, %f62 ! encoding: [0xbf,0xa0,0x48,0x43]
|
||||
! CHECK: faddq %f32, %f36, %f60 ! encoding: [0xbb,0xa0,0x48,0x65]
|
||||
! CHECK: faddd %f32, %f34, %f62 ! encoding: [0xbf,0xa0,0x48,0x43]
|
||||
! CHECK: faddq %f32, %f36, %f60 ! encoding: [0xbb,0xa0,0x48,0x65]
|
||||
faddd %f32, %f34, %f62
|
||||
faddq %f32, %f36, %f60
|
||||
|
||||
@ -103,23 +103,23 @@
|
||||
fcmpd %f0, %f4
|
||||
fcmpq %f0, %f4
|
||||
|
||||
! CHECK: fcmpes %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xa4]
|
||||
! CHECK: fcmped %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xc4]
|
||||
! CHECK: fcmpeq %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xe4]
|
||||
! CHECK: fcmpes %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xa4]
|
||||
! CHECK: fcmped %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xc4]
|
||||
! CHECK: fcmpeq %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xe4]
|
||||
fcmpes %f0, %f4
|
||||
fcmped %f0, %f4
|
||||
fcmpeq %f0, %f4
|
||||
|
||||
! CHECK: fcmps %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0x24]
|
||||
! CHECK: fcmpd %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0x44]
|
||||
! CHECK: fcmpq %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0x64]
|
||||
! CHECK: fcmps %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0x24]
|
||||
! CHECK: fcmpd %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0x44]
|
||||
! CHECK: fcmpq %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0x64]
|
||||
fcmps %fcc2, %f0, %f4
|
||||
fcmpd %fcc2, %f0, %f4
|
||||
fcmpq %fcc2, %f0, %f4
|
||||
|
||||
! CHECK: fcmpes %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0xa4]
|
||||
! CHECK: fcmped %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0xc4]
|
||||
! CHECK: fcmpeq %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0xe4]
|
||||
! CHECK: fcmpes %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0xa4]
|
||||
! CHECK: fcmped %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0xc4]
|
||||
! CHECK: fcmpeq %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0xe4]
|
||||
fcmpes %fcc2, %f0, %f4
|
||||
fcmped %fcc2, %f0, %f4
|
||||
fcmpeq %fcc2, %f0, %f4
|
||||
@ -147,3 +147,11 @@
|
||||
! CHECK: std %f48, [%l0] ! encoding: [0xe3,0x3c,0x00,0x00]
|
||||
st %f29, [%l0]
|
||||
std %f48, [%l0]
|
||||
|
||||
! CHECK: std %fq, [%o4] ! encoding: [0xc1,0x33,0x00,0x00]
|
||||
! CHECK: std %fq, [%l1+62] ! encoding: [0xc1,0x34,0x60,0x3e]
|
||||
! CHECK: std %fq, [%i3+%l7] ! encoding: [0xc1,0x36,0xc0,0x17]
|
||||
std %fq, [%o4]
|
||||
std %fq, [%l1+62]
|
||||
std %fq, [%i3+%l7]
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user