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[ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.

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llvm-svn: 205879
This commit is contained in:
Bradley Smith 2014-04-09 14:43:24 +00:00
parent 1828a1cae0
commit 5d3f0b60b1
2 changed files with 8 additions and 0 deletions
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6
lib/Target/ARM64/ARM64InstrFormats.td
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@ -1640,6 +1640,9 @@ multiclass BitfieldImm<bits<2> opc, string asm> {
def Wri : BaseBitfieldImm<opc, GPR32, imm0_31, asm> {
let Inst{31} = 0;
let Inst{22} = 0;
// imms<5> and immr<5> must be zero, else ReservedValue().
let Inst{21} = 0;
let Inst{15} = 0;
}
def Xri : BaseBitfieldImm<opc, GPR64, imm0_63, asm> {
let Inst{31} = 1;
@ -1671,6 +1674,9 @@ multiclass BitfieldImmWith2RegArgs<bits<2> opc, string asm> {
def Wri : BaseBitfieldImmWith2RegArgs<opc, GPR32, imm0_31, asm> {
let Inst{31} = 0;
let Inst{22} = 0;
// imms<5> and immr<5> must be zero, else ReservedValue().
let Inst{21} = 0;
let Inst{15} = 0;
}
def Xri : BaseBitfieldImmWith2RegArgs<opc, GPR64, imm0_63, asm> {
let Inst{31} = 1;

2
test/MC/Disassembler/ARM64/basic-a64-undefined.txt
View File

@ -17,5 +17,7 @@
# RUN: echo "0x00 0x00 0xc0 0xeb" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
# RUN: echo "0x00 0x80 0x80 0x6b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
# UBFM is undefined when s == 0 and imms<5> or immr<5> is 1.
# RUN: echo "0x00 0x80 0x00 0x53" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
# CHECK: invalid instruction encoding