RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-25 21:48:12 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Do the right thing and enable 64 bit regs under the control of a subtarget

Browse Source 
option.  Currently the only way to enable this is to specify the
64bitregs mattr flag.  It is never enabled by default on any config yet.

llvm-svn: 23779
This commit is contained in:
Nate Begeman 2005-10-18 00:56:42 +00:00
parent b0e319a7c7
commit 5dbcab491a
3 changed files with 10 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -94,19 +94,16 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
// 64 bit PowerPC implementations can support i64 types directly
// FIXME: enable this once it works.
//addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
// They also have instructions for converting between i64 and fp.
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
}
if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) {
// 64 bit PowerPC implementations can support i64 types directly
addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
// BUILD_PAIR can't be handled natively, and should be expanded to shl/or
setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
// 32 bit PowerPC wants to expand i64 shifts itself.
// FIXME: remove these once we natively handle i64 shifts.
setOperationAction(ISD::SHL, MVT::i64, Custom);
setOperationAction(ISD::SRL, MVT::i64, Custom);
setOperationAction(ISD::SRA, MVT::i64, Custom);
} else {
// 32 bit PowerPC wants to expand i64 shifts itself.
setOperationAction(ISD::SHL, MVT::i64, Custom);

3
lib/Target/PowerPC/PPCSubtarget.cpp
View File

@ -36,6 +36,7 @@ enum PowerPCFeature {
PowerPCFeatureAltivec = 1 << 1,
PowerPCFeatureFSqrt = 1 << 2,
PowerPCFeatureGPUL = 1 << 3,
PowerPCFeature64BRegs = 1 << 4
};
/// Sorted (by key) array of values for CPU subtype.
@ -73,6 +74,7 @@ static const unsigned PowerPCSubTypeKVSize = sizeof(PowerPCSubTypeKV)
/// Sorted (by key) array of values for CPU features.
static SubtargetFeatureKV PowerPCFeatureKV[] = {
{ "64bit" , "Should 64 bit instructions be used" , PowerPCFeature64Bit },
{ "64bitregs", "Should 64 bit registers be used" , PowerPCFeature64BRegs },
{ "altivec", "Should Altivec instructions be used" , PowerPCFeatureAltivec },
{ "fsqrt" , "Should the fsqrt instruction be used", PowerPCFeatureFSqrt },
{ "gpul" , "Should GPUL instructions be used" , PowerPCFeatureGPUL }
@ -134,6 +136,7 @@ PPCSubtarget::PPCSubtarget(const Module &M, const std::string &FS)
IsGigaProcessor = (Bits & PowerPCFeatureGPUL ) != 0;
Is64Bit = (Bits & PowerPCFeature64Bit) != 0;
HasFSQRT = (Bits & PowerPCFeatureFSqrt) != 0;
Has64BitRegs = (Bits & PowerPCFeature64BRegs) != 0;
// Set the boolean corresponding to the current target triple, or the default
// if one cannot be determined, to true.

2
lib/Target/PowerPC/PPCSubtarget.h
View File

@ -30,6 +30,7 @@ protected:
/// Used by the ISel to turn in optimizations for POWER4-derived architectures
bool IsGigaProcessor;
bool Is64Bit;
bool Has64BitRegs;
bool HasFSQRT;
bool IsAIX;
bool IsDarwin;
@ -49,6 +50,7 @@ public:
bool isAIX() const { return IsAIX; }
bool isDarwin() const { return IsDarwin; }
bool is64Bit() const { return Is64Bit; }
bool has64BitRegs() const { return Has64BitRegs; }
bool isGigaProcessor() const { return IsGigaProcessor; }
};
} // End llvm namespace