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Add cdp/cdp2 instructions for thumb/thumb2

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llvm-svn: 123929
This commit is contained in:
Bruno Cardoso Lopes 2011-01-20 18:32:09 +00:00
parent e3e6201a2f
commit 5f06c0aa3b
5 changed files with 57 additions and 1 deletions
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25
lib/Target/ARM/ARMInstrThumb.td
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@ -1377,6 +1377,31 @@ class tMovRRCopro<string opc, bit direction>
def tMCRR : tMovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>; def tMCRR : tMovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
def tMRRC : tMovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>; def tMRRC : tMovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
//===----------------------------------------------------------------------===//
// Other Coprocessor Instructions. For disassembly only.
//
def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
"cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
[/* For disassembly only; pattern left blank */]> {
let Inst{27-24} = 0b1110;
bits<4> opc1;
bits<4> CRn;
bits<4> CRd;
bits<4> cop;
bits<3> opc2;
bits<4> CRm;
let Inst{3-0} = CRm;
let Inst{4} = 0;
let Inst{7-5} = opc2;
let Inst{11-8} = cop;
let Inst{15-12} = CRd;
let Inst{19-16} = CRn;
let Inst{23-20} = opc1;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// TLS Instructions // TLS Instructions
// //

25
lib/Target/ARM/ARMInstrThumb2.td
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@ -3378,3 +3378,28 @@ class t2MovRRCopro<string opc, bit direction>
def t2MCRR : t2MovRRCopro<"mcrr2",0/* from ARM core register to coprocessor */>; def t2MCRR : t2MovRRCopro<"mcrr2",0/* from ARM core register to coprocessor */>;
def t2MRRC : t2MovRRCopro<"mrrc2",1/* from coprocessor to ARM core register */>; def t2MRRC : t2MovRRCopro<"mrrc2",1/* from coprocessor to ARM core register */>;
//===----------------------------------------------------------------------===//
// Other Coprocessor Instructions. For disassembly only.
//
def t2CDP2 : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
"cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
[/* For disassembly only; pattern left blank */]> {
let Inst{27-24} = 0b1110;
bits<4> opc1;
bits<4> CRn;
bits<4> CRd;
bits<4> cop;
bits<3> opc2;
bits<4> CRm;
let Inst{3-0} = CRm;
let Inst{4} = 0;
let Inst{7-5} = opc2;
let Inst{11-8} = cop;
let Inst{15-12} = CRd;
let Inst{19-16} = CRn;
let Inst{23-20} = opc1;
}

2
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -1202,7 +1202,7 @@ GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
if (isThumb) if (isThumb)
if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
Mnemonic == "mrc" || Mnemonic == "mrrc") Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
CanAcceptPredicationCode = false; CanAcceptPredicationCode = false;
} }

3
test/MC/ARM/thumb.s
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@ -51,3 +51,6 @@
@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x54,0xec,0x11,0x57] @ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x54,0xec,0x11,0x57]
mrrc p7, #1, r5, r4, c1 mrrc p7, #1, r5, r4, c1
@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x11,0xee,0x81,0x17]
cdp p7, #1, c1, c1, c1, #4

3
test/MC/ARM/thumb2.s
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@ -194,3 +194,6 @@
@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x54,0xfc,0x11,0x57] @ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x54,0xfc,0x11,0x57]
mrrc2 p7, #1, r5, r4, c1 mrrc2 p7, #1, r5, r4, c1
@ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x11,0xfe,0x81,0x17]
cdp2 p7, #1, c1, c1, c1, #4