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Targets all now request ConstantFP to be legalized into TargetConstantFP.
'fpimm' in .td files is now TargetConstantFP. llvm-svn: 25771
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@ -419,7 +419,7 @@ SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
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case ISD::SREM:
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case ISD::UREM: return SelectDIV(Op);
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case ISD::ConstantFP: {
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case ISD::TargetConstantFP: {
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SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
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if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0))
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@ -104,6 +104,7 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
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computeRegisterProperties();
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setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
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addLegalFPImmediate(+0.0);
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addLegalFPImmediate(+1.0);
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}
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@ -37,6 +37,9 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
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addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
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addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
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setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
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setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
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// PowerPC has no intrinsics for these particular operations
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setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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@ -194,7 +194,8 @@ def node;
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def srcvalue;
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def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
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def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
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def fpimm : SDNode<"ISD::TargetConstantFP",
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SDTFPLeaf, [], "ConstantFPSDNode">;
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def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
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def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
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def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
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@ -45,7 +45,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setSchedulingPreference(SchedulingForRegPressure);
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setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
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setStackPointerRegisterToSaveRestore(X86::ESP);
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// Set up the register classes.
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addRegisterClass(MVT::i8, X86::R8RegisterClass);
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addRegisterClass(MVT::i16, X86::R16RegisterClass);
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@ -213,6 +213,10 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::FNEG , MVT::f32, Expand);
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setOperationAction(ISD::FREM , MVT::f32, Expand);
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// Expand FP immediates into loads from the stack, except for the special
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// cases we handle.
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setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
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setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
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addLegalFPImmediate(+0.0); // xorps / xorpd
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} else {
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// Set up the FP register classes.
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@ -228,6 +232,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::FCOS , MVT::f64 , Expand);
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}
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setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
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addLegalFPImmediate(+0.0); // FLD0
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addLegalFPImmediate(+1.0); // FLD1
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addLegalFPImmediate(-0.0); // FLD0/FCHS
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