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Coalesce insert_subreg undef, x first to avoid phase ordering issue.
llvm-svn: 91103
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@ -745,8 +745,16 @@ unsigned LiveIntervals::getVNInfoSourceReg(const VNInfo *VNI) const {
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if (VNI->getCopy()->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
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if (VNI->getCopy()->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
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// If it's extracting out of a physical register, return the sub-register.
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// If it's extracting out of a physical register, return the sub-register.
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unsigned Reg = VNI->getCopy()->getOperand(1).getReg();
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unsigned Reg = VNI->getCopy()->getOperand(1).getReg();
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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unsigned SrcSubReg = VNI->getCopy()->getOperand(2).getImm();
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unsigned DstSubReg = VNI->getCopy()->getOperand(0).getSubReg();
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if (SrcSubReg == DstSubReg)
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// %reg1034:3<def> = EXTRACT_SUBREG %EDX, 3
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// reg1034 can still be coalesced to EDX.
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return Reg;
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assert(DstSubReg == 0);
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Reg = tri_->getSubReg(Reg, VNI->getCopy()->getOperand(2).getImm());
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Reg = tri_->getSubReg(Reg, VNI->getCopy()->getOperand(2).getImm());
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}
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return Reg;
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return Reg;
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} else if (VNI->getCopy()->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
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} else if (VNI->getCopy()->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
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VNI->getCopy()->getOpcode() == TargetInstrInfo::SUBREG_TO_REG)
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VNI->getCopy()->getOpcode() == TargetInstrInfo::SUBREG_TO_REG)
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@ -2422,9 +2422,15 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
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// If this isn't a copy nor a extract_subreg, we can't join intervals.
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// If this isn't a copy nor a extract_subreg, we can't join intervals.
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unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
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unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
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bool isInsUndef = false;
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if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
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if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
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DstReg = Inst->getOperand(0).getReg();
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DstReg = Inst->getOperand(0).getReg();
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SrcReg = Inst->getOperand(1).getReg();
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SrcReg = Inst->getOperand(1).getReg();
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} else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
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DstReg = Inst->getOperand(0).getReg();
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SrcReg = Inst->getOperand(2).getReg();
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if (Inst->getOperand(1).isUndef())
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isInsUndef = true;
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} else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
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} else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
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Inst->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
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Inst->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
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DstReg = Inst->getOperand(0).getReg();
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DstReg = Inst->getOperand(0).getReg();
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@ -2434,7 +2440,8 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
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bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
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bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
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bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
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bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
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if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
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if (isInsUndef ||
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(li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty()))
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ImpDefCopies.push_back(CopyRec(Inst, 0));
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ImpDefCopies.push_back(CopyRec(Inst, 0));
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else if (SrcIsPhys || DstIsPhys)
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else if (SrcIsPhys || DstIsPhys)
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PhysCopies.push_back(CopyRec(Inst, 0));
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PhysCopies.push_back(CopyRec(Inst, 0));
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@ -2442,9 +2449,9 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
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VirtCopies.push_back(CopyRec(Inst, 0));
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VirtCopies.push_back(CopyRec(Inst, 0));
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}
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}
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// Try coalescing implicit copies first, followed by copies to / from
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// Try coalescing implicit copies and insert_subreg <undef> first,
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// physical registers, then finally copies from virtual registers to
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// followed by copies to / from physical registers, then finally copies
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// virtual registers.
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// from virtual registers to virtual registers.
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for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
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for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
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CopyRec &TheCopy = ImpDefCopies[i];
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CopyRec &TheCopy = ImpDefCopies[i];
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bool Again = false;
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bool Again = false;
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