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add support for div/rem to the dag->dag isel. yay.
llvm-svn: 24472
This commit is contained in:
Duraid Madina
parent
04be8e167c
commit
5fe9d39b8d
@ -93,6 +93,7 @@ namespace {
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#include "IA64GenDAGISel.inc"
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private:
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SDOperand SelectDIV(SDOperand Op);
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SDOperand SelectCALL(SDOperand Op);
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};
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}
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@ -153,6 +154,179 @@ void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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ScheduleAndEmitDAG(DAG);
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}
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SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
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SDNode *N = Op.Val;
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SDOperand Chain = Select(N->getOperand(0));
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SDOperand Tmp1 = Select(N->getOperand(0));
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SDOperand Tmp2 = Select(N->getOperand(1));
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bool isFP=false;
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if(MVT::isFloatingPoint(Tmp1.getValueType()))
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isFP=true;
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bool isModulus=false; // is it a division or a modulus?
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bool isSigned=false;
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switch(N->getOpcode()) {
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case ISD::FDIV:
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case ISD::SDIV: isModulus=false; isSigned=true; break;
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case ISD::UDIV: isModulus=false; isSigned=false; break;
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case ISD::FREM:
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case ISD::SREM: isModulus=true; isSigned=true; break;
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case ISD::UREM: isModulus=true; isSigned=false; break;
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}
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// TODO: check for integer divides by powers of 2 (or other simple patterns?)
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SDOperand TmpPR, TmpPR2;
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SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
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SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
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SDOperand Result;
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// OK, emit some code:
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if(!isFP) {
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// first, load the inputs into FP regs.
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TmpF1 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1);
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Chain = TmpF1.getValue(1);
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TmpF2 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2);
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Chain = TmpF2.getValue(1);
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// next, convert the inputs to FP
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if(isSigned) {
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TmpF3 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1);
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Chain = TmpF3.getValue(1);
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TmpF4 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2);
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Chain = TmpF4.getValue(1);
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} else {
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TmpF3 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
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Chain = TmpF3.getValue(1);
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TmpF4 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
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Chain = TmpF4.getValue(1);
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}
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} else { // this is an FP divide/remainder, so we 'leak' some temp
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// regs and assign TmpF3=Tmp1, TmpF4=Tmp2
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TmpF3=Tmp1;
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TmpF4=Tmp2;
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}
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// we start by computing an approximate reciprocal (good to 9 bits?)
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// note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
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TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
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TmpF3, TmpF4);
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TmpPR = TmpF5.getValue(1);
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Chain = TmpF5.getValue(2);
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if(!isModulus) { // if this is a divide, we worry about div-by-zero
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SDOperand bogusPR = CurDAG->getTargetNode(IA64::CMPEQ, MVT::i1,
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CurDAG->getRegister(IA64::r0, MVT::i64),
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CurDAG->getRegister(IA64::r0, MVT::i64));
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Chain = bogusPR.getValue(1);
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TmpPR2 = CurDAG->getTargetNode(IA64::TPCMPNE, MVT::i1, bogusPR,
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CurDAG->getRegister(IA64::r0, MVT::i64),
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CurDAG->getRegister(IA64::r0, MVT::i64), TmpPR);
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Chain = TmpPR2.getValue(1);
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}
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SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
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SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
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// now we apply newton's method, thrice! (FIXME: this is ~72 bits of
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// precision, don't need this much for f32/i32)
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TmpF6 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
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TmpF4, TmpF5, F1, TmpPR);
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Chain = TmpF6.getValue(1);
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TmpF7 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpF3, TmpF5, F0, TmpPR);
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Chain = TmpF7.getValue(1);
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TmpF8 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpF6, TmpF6, F0, TmpPR);
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Chain = TmpF8.getValue(1);
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TmpF9 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpF6, TmpF7, TmpF7, TmpPR);
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Chain = TmpF9.getValue(1);
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TmpF10 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpF6, TmpF5, TmpF5, TmpPR);
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Chain = TmpF10.getValue(1);
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TmpF11 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpF8, TmpF9, TmpF9, TmpPR);
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Chain = TmpF11.getValue(1);
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TmpF12 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpF8, TmpF10, TmpF10, TmpPR);
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Chain = TmpF12.getValue(1);
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TmpF13 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
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TmpF4, TmpF11, TmpF3, TmpPR);
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Chain = TmpF13.getValue(1);
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// FIXME: this is unfortunate :(
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// the story is that the dest reg of the fnma above and the fma below
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// (and therefore possibly the src of the fcvt.fx[u] as well) cannot
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// be the same register, or this code breaks if the first argument is
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// zero. (e.g. without this hack, 0%8 yields -64, not 0.)
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TmpF14 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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TmpF13, TmpF12, TmpF11, TmpPR);
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Chain = TmpF14.getValue(1);
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if(isModulus) { // XXX: fragile! fixes _only_ mod, *breaks* div! !
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SDOperand bogus = CurDAG->getTargetNode(IA64::IUSE, MVT::Other, TmpF13); // hack :(
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Chain = bogus.getValue(0); // hmmm
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}
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if(!isFP) {
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// round to an integer
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if(isSigned) {
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TmpF15 = CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, MVT::i64, TmpF14);
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Chain = TmpF15.getValue(1);
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}
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else {
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TmpF15 = CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, MVT::i64, TmpF14);
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Chain = TmpF15.getValue(1);
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}
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} else {
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TmpF15 = TmpF14;
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// EXERCISE: can you see why TmpF15=TmpF14 does not work here, and
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// we really do need the above FMOV? ;)
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}
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if(!isModulus) {
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if(isFP) { // extra worrying about div-by-zero
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// we do a 'conditional fmov' (of the correct result, depending
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// on how the frcpa predicate turned out)
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SDOperand bogoResult = CurDAG->getTargetNode(IA64::PFMOV, MVT::f64,
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TmpF12, TmpPR2);
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Chain = bogoResult.getValue(1);
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Result = CurDAG->getTargetNode(IA64::CFMOV, MVT::f64, bogoResult,
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TmpF15, TmpPR);
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Chain = Result.getValue(1);
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}
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else {
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Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpF15);
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Chain = Result.getValue(1);
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}
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} else { // this is a modulus
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if(!isFP) {
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// answer = q * (-b) + a
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SDOperand TmpI = CurDAG->getTargetNode(IA64::SUB, MVT::i64,
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CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2);
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Chain = TmpI.getValue(1);
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SDOperand TmpF = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, TmpI);
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Chain = TmpF.getValue(1);
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SDOperand ModulusResult = CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
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TmpF15, TmpF, TmpF1);
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Chain = ModulusResult.getValue(1);
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Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, ModulusResult);
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Chain = Result.getValue(1);
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} else { // FP modulus! The horror... the horror....
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assert(0 && "sorry, no FP modulus just yet!\n!\n");
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}
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}
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return Result;
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}
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SDOperand IA64DAGToDAGISel::SelectCALL(SDOperand Op) {
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SDNode *N = Op.Val;
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@ -355,6 +529,12 @@ SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
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case ISD::CALL:
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case ISD::TAILCALL: return SelectCALL(Op);
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case ISD::FDIV:
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::SREM:
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case ISD::UREM: return SelectDIV(Op);
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/* todo:
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* case ISD::DYNAMIC_STACKALLOC:
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