- Have "ADD" instructions return an implicit EFLAGS.

- Add support for seto, setno, setc, and setnc instructions.

llvm-svn: 60382

lib/Target/X86/X86Instr64bit.td

@@ -314,59 +314,73 @@ let isConvertibleToThreeAddress = 1 in {
 let isCommutable = 1 in
 def ADD64rr  : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
                   "add{q}\t{$src2, $dst|$dst, $src2}",
-                  [(set GR64:$dst, (add GR64:$src1, GR64:$src2))]>;
+                  [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
+                   (implicit EFLAGS)]>;
 
 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
                       "add{q}\t{$src2, $dst|$dst, $src2}",
-                      [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2))]>;
+                      [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
+                       (implicit EFLAGS)]>;
 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
                     "add{q}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2))]>;
+                    [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
+                     (implicit EFLAGS)]>;
 } // isConvertibleToThreeAddress
 
 def ADD64rm  : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
                   "add{q}\t{$src2, $dst|$dst, $src2}",
-                  [(set GR64:$dst, (add GR64:$src1, (load addr:$src2)))]>;
+                  [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
+                   (implicit EFLAGS)]>;
 } // isTwoAddress
 
 def ADD64mr  : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
                   "add{q}\t{$src2, $dst|$dst, $src2}",
-                  [(store (add (load addr:$dst), GR64:$src2), addr:$dst)]>;
+                  [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
+                   (implicit EFLAGS)]>;
 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
                       "add{q}\t{$src2, $dst|$dst, $src2}",
-               [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
+               [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
+                (implicit EFLAGS)]>;
 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
                     "add{q}\t{$src2, $dst|$dst, $src2}",
-                [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
+                [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
+                 (implicit EFLAGS)]>;
 
 let Uses = [EFLAGS] in {
 let isTwoAddress = 1 in {
 let isCommutable = 1 in
 def ADC64rr  : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
                   "adc{q}\t{$src2, $dst|$dst, $src2}",
-                  [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
+                  [(set GR64:$dst, (adde GR64:$src1, GR64:$src2)),
+                   (implicit EFLAGS)]>;
 
 def ADC64rm  : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
                   "adc{q}\t{$src2, $dst|$dst, $src2}",
-                  [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
+                  [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2))),
+                   (implicit EFLAGS)]>;
 
 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
                       "adc{q}\t{$src2, $dst|$dst, $src2}",
-                      [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
+                      [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2)),
+                       (implicit EFLAGS)]>;
 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
                     "adc{q}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
+                    [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2)),
+                     (implicit EFLAGS)]>;
 } // isTwoAddress
 
 def ADC64mr  : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
                   "adc{q}\t{$src2, $dst|$dst, $src2}",
-                  [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
+                  [(store (adde (load addr:$dst), GR64:$src2), addr:$dst),
+                   (implicit EFLAGS)]>;
 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
                       "adc{q}\t{$src2, $dst|$dst, $src2}",
-               [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
+                 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst),
+                  (implicit EFLAGS)]>;
 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
                     "adc{q}\t{$src2, $dst|$dst, $src2}",
-               [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
+                 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst),
+                   (implicit EFLAGS)]>;
 } // Uses = [EFLAGS]
 
 let isTwoAddress = 1 in {

lib/Target/X86/X86InstrInfo.cpp

@@ -280,14 +280,18 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
     { X86::SETAr,       X86::SETAm, 0 },
     { X86::SETBEr,      X86::SETBEm, 0 },
     { X86::SETBr,       X86::SETBm, 0 },
+    { X86::SETCr,       X86::SETCm, 0 },
     { X86::SETEr,       X86::SETEm, 0 },
     { X86::SETGEr,      X86::SETGEm, 0 },
     { X86::SETGr,       X86::SETGm, 0 },
     { X86::SETLEr,      X86::SETLEm, 0 },
     { X86::SETLr,       X86::SETLm, 0 },
+    { X86::SETNCr,      X86::SETNCm, 0 },
     { X86::SETNEr,      X86::SETNEm, 0 },
+    { X86::SETNOr,      X86::SETNOm, 0 },
     { X86::SETNPr,      X86::SETNPm, 0 },
     { X86::SETNSr,      X86::SETNSm, 0 },
+    { X86::SETOr,       X86::SETOm, 0 },
     { X86::SETPr,       X86::SETPm, 0 },
     { X86::SETSr,       X86::SETSm, 0 },
     { X86::TAILJMPr,    X86::TAILJMPm, 1 },

lib/Target/X86/X86InstrInfo.td

@@ -1926,110 +1926,136 @@ let isCommutable = 1 in {   // X = ADD Y, Z   --> X = ADD Z, Y
 def ADD8rr   : I<0x00, MRMDestReg, (outs GR8 :$dst),
                                    (ins GR8 :$src1, GR8 :$src2),
                  "add{b}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
+                 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
+                  (implicit EFLAGS)]>;
 let isConvertibleToThreeAddress = 1 in {   // Can transform into LEA.
 def ADD16rr  : I<0x01, MRMDestReg, (outs GR16:$dst),
                                    (ins GR16:$src1, GR16:$src2),
                  "add{w}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
+                 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
+                  (implicit EFLAGS)]>, OpSize;
 def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst),
                                    (ins GR32:$src1, GR32:$src2),
                  "add{l}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
+                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
+                  (implicit EFLAGS)]>;
 } // end isConvertibleToThreeAddress
 } // end isCommutable
 def ADD8rm   : I<0x02, MRMSrcMem, (outs GR8 :$dst),
                                   (ins GR8 :$src1, i8mem :$src2),
                  "add{b}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
+                 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
+                  (implicit EFLAGS)]>;
 def ADD16rm  : I<0x03, MRMSrcMem, (outs GR16:$dst),
                                   (ins GR16:$src1, i16mem:$src2),
                  "add{w}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>,OpSize;
+                 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
+                  (implicit EFLAGS)]>, OpSize;
 def ADD32rm  : I<0x03, MRMSrcMem, (outs GR32:$dst),
                                   (ins GR32:$src1, i32mem:$src2),
                  "add{l}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
+                 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
+                  (implicit EFLAGS)]>;
 
 def ADD8ri   : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
                    "add{b}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
+                   [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
+                    (implicit EFLAGS)]>;
 
 let isConvertibleToThreeAddress = 1 in {   // Can transform into LEA.
 def ADD16ri  : Ii16<0x81, MRM0r, (outs GR16:$dst),
                                  (ins GR16:$src1, i16imm:$src2),
                     "add{w}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
+                    [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
+                     (implicit EFLAGS)]>, OpSize;
 def ADD32ri  : Ii32<0x81, MRM0r, (outs GR32:$dst),
                                  (ins GR32:$src1, i32imm:$src2),
                     "add{l}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
+                    [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
+                     (implicit EFLAGS)]>;
 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
                                 (ins GR16:$src1, i16i8imm:$src2),
                    "add{w}\t{$src2, $dst|$dst, $src2}",
-                [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, OpSize;
+                [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
+                 (implicit EFLAGS)]>, OpSize;
 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
                                 (ins GR32:$src1, i32i8imm:$src2),
                    "add{l}\t{$src2, $dst|$dst, $src2}",
-                [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
+                [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
+                 (implicit EFLAGS)]>;
 }
 
 let isTwoAddress = 0 in {
   def ADD8mr   : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
                    "add{b}\t{$src2, $dst|$dst, $src2}",
-                   [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
+                   [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
+                    (implicit EFLAGS)]>;
   def ADD16mr  : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
                    "add{w}\t{$src2, $dst|$dst, $src2}",
-                   [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
+                   [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
+                    (implicit EFLAGS)]>,
                  OpSize;
   def ADD32mr  : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
                    "add{l}\t{$src2, $dst|$dst, $src2}",
-                   [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
+                   [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
+                    (implicit EFLAGS)]>;
   def ADD8mi   : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
                      "add{b}\t{$src2, $dst|$dst, $src2}",
-                   [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
+                   [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
+                    (implicit EFLAGS)]>;
   def ADD16mi  : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
                       "add{w}\t{$src2, $dst|$dst, $src2}",
-                  [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
+                  [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
+                   (implicit EFLAGS)]>,
                  OpSize;
   def ADD32mi  : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
                       "add{l}\t{$src2, $dst|$dst, $src2}",
-                  [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
+                  [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
+                   (implicit EFLAGS)]>;
   def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
                      "add{w}\t{$src2, $dst|$dst, $src2}",
-                [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
+                  [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst),
+                   (implicit EFLAGS)]>,
                  OpSize;
   def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
                      "add{l}\t{$src2, $dst|$dst, $src2}",
-                [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
+                  [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst),
+                   (implicit EFLAGS)]>;
 }
 
 let Uses = [EFLAGS] in {
 let isCommutable = 1 in {  // X = ADC Y, Z --> X = ADC Z, Y
 def ADC32rr  : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                  "adc{l}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
+                 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2)),
+                  (implicit EFLAGS)]>;
 }
 def ADC32rm  : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
                  "adc{l}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
+                 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2))),
+                  (implicit EFLAGS)]>;
 def ADC32ri  : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
                     "adc{l}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
+                 [(set GR32:$dst, (adde GR32:$src1, imm:$src2)),
+                  (implicit EFLAGS)]>;
 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
                    "adc{l}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
+                 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2)),
+                  (implicit EFLAGS)]>;
 
 let isTwoAddress = 0 in {
   def ADC32mr  : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
                    "adc{l}\t{$src2, $dst|$dst, $src2}",
-                   [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
+                   [(store (adde (load addr:$dst), GR32:$src2), addr:$dst),
+                    (implicit EFLAGS)]>;
   def ADC32mi  : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
                       "adc{l}\t{$src2, $dst|$dst, $src2}",
-                  [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
+                  [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst),
+                   (implicit EFLAGS)]>;
   def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
                      "adc{l}\t{$src2, $dst|$dst, $src2}",
-             [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
+                 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst),
+                  (implicit EFLAGS)]>;
 }
 } // Uses = [EFLAGS]
 
@@ -2272,6 +2298,7 @@ def SETEm    : I<0x94, MRM0m,
                  "sete\t$dst",
                  [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
                TB;                        // [mem8] = ==
+
 def SETNEr   : I<0x95, MRM0r, 
                  (outs GR8   :$dst), (ins),
                  "setne\t$dst",
@@ -2282,6 +2309,7 @@ def SETNEm   : I<0x95, MRM0m,
                  "setne\t$dst",
                  [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
                TB;                        // [mem8] = !=
+
 def SETLr    : I<0x9C, MRM0r, 
                  (outs GR8   :$dst), (ins),
                  "setl\t$dst",
@@ -2292,6 +2320,7 @@ def SETLm    : I<0x9C, MRM0m,
                  "setl\t$dst",
                  [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
                TB;                        // [mem8] = <  signed
+
 def SETGEr   : I<0x9D, MRM0r, 
                  (outs GR8   :$dst), (ins),
                  "setge\t$dst",
@@ -2302,6 +2331,7 @@ def SETGEm   : I<0x9D, MRM0m,
                  "setge\t$dst",
                  [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
                TB;                        // [mem8] = >= signed
+
 def SETLEr   : I<0x9E, MRM0r, 
                  (outs GR8   :$dst), (ins),
                  "setle\t$dst",
@@ -2312,6 +2342,7 @@ def SETLEm   : I<0x9E, MRM0m,
                  "setle\t$dst",
                  [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
                TB;                        // [mem8] = <= signed
+
 def SETGr    : I<0x9F, MRM0r, 
                  (outs GR8   :$dst), (ins),
                  "setg\t$dst",
@@ -2333,6 +2364,7 @@ def SETBm    : I<0x92, MRM0m,
                  "setb\t$dst",
                  [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
                TB;                        // [mem8] = <  unsign
+
 def SETAEr   : I<0x93, MRM0r, 
                  (outs GR8   :$dst), (ins),
                  "setae\t$dst",
@@ -2343,6 +2375,7 @@ def SETAEm   : I<0x93, MRM0m,
                  "setae\t$dst",
                  [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
                TB;                        // [mem8] = >= unsign
+
 def SETBEr   : I<0x96, MRM0r, 
                  (outs GR8   :$dst), (ins),
                  "setbe\t$dst",
@@ -2353,6 +2386,7 @@ def SETBEm   : I<0x96, MRM0m,
                  "setbe\t$dst",
                  [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
                TB;                        // [mem8] = <= unsign
+
 def SETAr    : I<0x97, MRM0r, 
                  (outs GR8   :$dst), (ins),
                  "seta\t$dst",
@@ -2384,6 +2418,7 @@ def SETNSm   : I<0x99, MRM0m,
                  "setns\t$dst",
                  [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
                TB;                        // [mem8] = !<sign bit>
+
 def SETPr    : I<0x9A, MRM0r, 
                  (outs GR8   :$dst), (ins),
                  "setp\t$dst",
@@ -2404,6 +2439,48 @@ def SETNPm   : I<0x9B, MRM0m,
                  "setnp\t$dst",
                  [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
                TB;                        // [mem8] = not parity
+
+def SETOr    : I<0x90, MRM0r, 
+                 (outs GR8   :$dst), (ins),
+                 "seto\t$dst",
+                 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
+               TB;                        // GR8 = overflow
+def SETOm    : I<0x90, MRM0m, 
+                 (outs), (ins i8mem:$dst),
+                 "seto\t$dst",
+                 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
+               TB;                        // [mem8] = overflow
+def SETNOr   : I<0x91, MRM0r, 
+                 (outs GR8   :$dst), (ins),
+                 "setno\t$dst",
+                 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
+               TB;                        // GR8 = not overflow
+def SETNOm   : I<0x91, MRM0m, 
+                 (outs), (ins i8mem:$dst),
+                 "setno\t$dst",
+                 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
+               TB;                        // [mem8] = not overflow
+
+def SETCr    : I<0x92, MRM0r, 
+                 (outs GR8   :$dst), (ins),
+                 "setc\t$dst",
+                 [(set GR8:$dst, (X86setcc X86_COND_C, EFLAGS))]>,
+               TB;                        // GR8 = carry
+def SETCm    : I<0x92, MRM0m, 
+                 (outs), (ins i8mem:$dst),
+                 "setc\t$dst",
+                 [(store (X86setcc X86_COND_C, EFLAGS), addr:$dst)]>,
+               TB;                        // [mem8] = carry
+def SETNCr   : I<0x93, MRM0r, 
+                 (outs GR8   :$dst), (ins),
+                 "setnc\t$dst",
+                 [(set GR8:$dst, (X86setcc X86_COND_NC, EFLAGS))]>,
+               TB;                        // GR8 = not carry
+def SETNCm   : I<0x93, MRM0m, 
+                 (outs), (ins i8mem:$dst),
+                 "setnc\t$dst",
+                 [(store (X86setcc X86_COND_NC, EFLAGS), addr:$dst)]>,
+               TB;                        // [mem8] = not carry
 } // Uses = [EFLAGS]