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[mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions
Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
This commit is contained in:
Hrvoje Varga
parent
e31be9c68b
commit
62d5d2ff36
@ -3722,6 +3722,7 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
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// and registers Rd and Base for microMIPS lwp instruction
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case Mips::JALR_HB:
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case Mips::JALRC_HB_MMR6:
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case Mips::JALRC_MMR6:
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if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())
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return Match_RequiresDifferentSrcAndDst;
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return Match_Success;
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@ -432,11 +432,21 @@ static DecodeStatus
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DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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template <typename InsnType>
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static DecodeStatus
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DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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template <typename InsnType>
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static DecodeStatus
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DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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template <typename InsnType>
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static DecodeStatus
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DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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template <typename InsnType>
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static DecodeStatus
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DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
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@ -603,6 +613,37 @@ static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
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return MCDisassembler::Success;
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}
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template <typename InsnType>
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static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
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uint64_t Address,
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const void *Decoder) {
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InsnType Rt = fieldFromInstruction(insn, 21, 5);
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InsnType Rs = fieldFromInstruction(insn, 16, 5);
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InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2;
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if (Rs >= Rt) {
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MI.setOpcode(Mips::BOVC_MMR6);
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
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Rt)));
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
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Rs)));
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} else if (Rs != 0 && Rs < Rt) {
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MI.setOpcode(Mips::BEQC_MMR6);
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
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Rs)));
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
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Rt)));
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} else {
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MI.setOpcode(Mips::BEQZALC_MMR6);
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
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Rt)));
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}
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MI.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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template <typename InsnType>
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static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
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uint64_t Address,
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@ -642,6 +683,37 @@ static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
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return MCDisassembler::Success;
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}
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template <typename InsnType>
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static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
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uint64_t Address,
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const void *Decoder) {
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InsnType Rt = fieldFromInstruction(insn, 21, 5);
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InsnType Rs = fieldFromInstruction(insn, 16, 5);
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InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2;
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if (Rs >= Rt) {
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MI.setOpcode(Mips::BNVC_MMR6);
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
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Rt)));
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
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Rs)));
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} else if (Rs != 0 && Rs < Rt) {
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MI.setOpcode(Mips::BNEC_MMR6);
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
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Rs)));
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
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Rt)));
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} else {
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MI.setOpcode(Mips::BNEZALC_MMR6);
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
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Rt)));
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}
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MI.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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template <typename InsnType>
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static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
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uint64_t Address,
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@ -124,6 +124,10 @@ void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
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} else if (Inst.getOpcode() == Mips::BNVC || Inst.getOpcode() == Mips::BOVC) {
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if (Reg0 >= Reg1)
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return;
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} else if (Inst.getOpcode() == Mips::BNVC_MMR6 ||
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Inst.getOpcode() == Mips::BOVC_MMR6) {
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if (Reg1 >= Reg0)
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return;
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} else
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llvm_unreachable("Cannot rewrite unknown branch!");
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@ -191,7 +195,9 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS,
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case Mips::BEQC:
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case Mips::BNEC:
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case Mips::BOVC:
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case Mips::BOVC_MMR6:
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case Mips::BNVC:
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case Mips::BNVC_MMR6:
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LowerCompactBranch(TmpInst);
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}
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@ -286,6 +292,30 @@ getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo,
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return 0;
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}
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/// getBranchTargetOpValueMMR6 - Return binary encoding of the branch
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/// target operand. If the machine operand requires relocation,
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/// record the relocation and return zero.
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unsigned MipsMCCodeEmitter::
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getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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// If the destination is an immediate, divide by 2.
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if (MO.isImm())
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return MO.getImm() >> 1;
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assert(MO.isExpr() &&
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"getBranchTargetOpValueMMR6 expects only expressions or immediates");
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const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
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MO.getExpr(), MCConstantExpr::create(-2, Ctx), Ctx);
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Fixups.push_back(MCFixup::create(0, FixupExpression,
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MCFixupKind(Mips::fixup_Mips_PC16)));
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return 0;
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}
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/// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch
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/// target operand. If the machine operand requires relocation,
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/// record the relocation and return zero.
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@ -109,6 +109,13 @@ public:
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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// getBranchTargetOpValueMMR6 - Return binary encoding of the branch
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// target operand. If the machine operand requires relocation,
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// record the relocation and return zero.
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unsigned getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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// getBranchTarget7OpValue - Return binary encoding of the microMIPS branch
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// target operand. If the machine operand requires relocation,
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// record the relocation and return zero.
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@ -71,6 +71,32 @@ class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
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let Inst{4-0} = op;
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}
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class POP35_BOVC_FM_MMR6<string instr_asm> : MipsR6Inst, MMR6Arch<instr_asm> {
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bits<5> rt;
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bits<5> rs;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = 0b011101;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-0} = offset;
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}
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class POP37_BNVC_FM_MMR6<string instr_asm> : MipsR6Inst, MMR6Arch<instr_asm> {
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bits<5> rt;
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bits<5> rs;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = 0b011111;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-0} = offset;
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}
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class POOL16C_JRCADDIUSP_FM_MM16R6<bits<5> op> {
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bits<5> imm;
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@ -508,6 +534,23 @@ class POOL32A_JALRC_FM_MMR6<string instr_asm, bits<10> funct>
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let Inst{5-0} = 0b111100;
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}
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class POOL32A_EXT_INS_FM_MMR6<string instr_asm, bits<6> funct>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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bits<5> rt;
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bits<5> rs;
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bits<5> size;
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bits<5> pos;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-11} = size;
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let Inst{10-6} = pos;
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let Inst{5-0} = funct;
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}
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class POOL32A_ERET_FM_MMR6<string instr_asm, bits<10> funct>
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: MMR6Arch<instr_asm> {
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bits<32> Inst;
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@ -25,6 +25,13 @@ def brtarget26_mm : Operand<OtherVT> {
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let ParserMatchClass = MipsJumpTargetAsmOperand;
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}
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def brtargetr6 : Operand<OtherVT> {
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let EncoderMethod = "getBranchTargetOpValueMMR6";
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let OperandType = "OPERAND_PCREL";
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let DecoderMethod = "DecodeBranchTargetMM";
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let ParserMatchClass = MipsJumpTargetAsmOperand;
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}
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//===----------------------------------------------------------------------===//
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//
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// Instruction Encodings
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@ -190,7 +197,11 @@ class SELNEZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.s", 0, 0b001111000>;
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class SELNEZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.d", 1, 0b001111000>;
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class CLASS_S_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.s", 0, 0b001100000>;
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class CLASS_D_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.d", 1, 0b001100000>;
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class EXT_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ext", 0b101100>;
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class INS_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ins", 0b001100>;
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class JALRC_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc", 0b0000111100>;
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class BOVC_MMR6_ENC : POP35_BOVC_FM_MMR6<"bovc">;
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class BNVC_MMR6_ENC : POP37_BNVC_FM_MMR6<"bnvc">;
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class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
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class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
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class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16;
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@ -1193,6 +1204,53 @@ class BRANCH_COP2_MMR6_DESC_BASE<string opstr> : BRANCH_DESC_BASE {
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class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc">;
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class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc">;
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class EXT_MMR6_DESC {
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dag OutOperandList = (outs GPR32Opnd:$rt);
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dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_plus1:$size);
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string AsmString = !strconcat("ext", "\t$rt, $rs, $pos, $size");
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list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsExt GPR32Opnd:$rs, imm:$pos,
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imm:$size))];
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InstrItinClass Itinerary = II_EXT;
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Format Form = FrmR;
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string BaseOpcode = "ext";
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}
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class INS_MMR6_DESC {
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dag OutOperandList = (outs GPR32Opnd:$rt);
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dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_inssize_plus1:$size,
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GPR32Opnd:$src);
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string AsmString = !strconcat("ins", "\t$rt, $rs, $pos, $size");
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list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsIns GPR32Opnd:$rs, imm:$pos,
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imm:$size, GPR32Opnd:$src))];
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InstrItinClass Itinerary = II_INS;
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Format Form = FrmR;
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string BaseOpcode = "ins";
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string Constraints = "$src = $rt";
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}
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class JALRC_MMR6_DESC {
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dag OutOperandList = (outs GPR32Opnd:$rt);
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dag InOperandList = (ins GPR32Opnd:$rs);
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string AsmString = !strconcat("jalrc", "\t$rt, $rs");
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list<dag> Pattern = [];
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InstrItinClass Itinerary = II_JALRC;
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bit isCall = 1;
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bit hasDelaySlot = 0;
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list<Register> Defs = [RA];
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}
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class BOVC_BNVC_MMR6_DESC_BASE<string instr_asm, Operand opnd,
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RegisterOperand GPROpnd>
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: BRANCH_DESC_BASE {
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dag InOperandList = (ins GPROpnd:$rt, GPROpnd:$rs, opnd:$offset);
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dag OutOperandList = (outs);
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string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $offset");
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list<Register> Defs = [AT];
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}
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class BOVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bovc", brtargetr6, GPR32Opnd>;
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class BNVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bnvc", brtargetr6, GPR32Opnd>;
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//===----------------------------------------------------------------------===//
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//
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// Instruction Definitions
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@ -1464,6 +1522,9 @@ def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
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ISA_MICROMIPS32R6;
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def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def EXT_MMR6 : StdMMR6Rel, EXT_MMR6_ENC, EXT_MMR6_DESC, ISA_MICROMIPS32R6;
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def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6;
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def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6;
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def RECIP_S_MMR6 : StdMMR6Rel, RECIP_S_MMR6_ENC, RECIP_S_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def RECIP_D_MMR6 : StdMMR6Rel, RECIP_D_MMR6_ENC, RECIP_D_MMR6_DESC, ISA_MICROMIPS32R6;
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@ -1508,12 +1569,18 @@ def BC2NEZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2NEZC_MMR6_ENC, BC2NEZC_MMR6_DESC,
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ISA_MICROMIPS32R6;
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}
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def BOVC_MMR6 : R6MMR6Rel, BOVC_MMR6_ENC, BOVC_MMR6_DESC, ISA_MICROMIPS32R6,
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MMDecodeDisambiguatedBy<"POP35GroupBranchMMR6">;
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def BNVC_MMR6 : R6MMR6Rel, BNVC_MMR6_ENC, BNVC_MMR6_DESC, ISA_MICROMIPS32R6,
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MMDecodeDisambiguatedBy<"POP37GroupBranchMMR6">;
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def BGEC_MMR6 : R6MMR6Rel, BGEC_MMR6_ENC, BGEC_MMR6_DESC, ISA_MICROMIPS32R6;
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def BGEUC_MMR6 : R6MMR6Rel, BGEUC_MMR6_ENC, BGEUC_MMR6_DESC, ISA_MICROMIPS32R6;
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def BLTC_MMR6 : R6MMR6Rel, BLTC_MMR6_ENC, BLTC_MMR6_DESC, ISA_MICROMIPS32R6;
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def BLTUC_MMR6 : R6MMR6Rel, BLTUC_MMR6_ENC, BLTUC_MMR6_DESC, ISA_MICROMIPS32R6;
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def BEQC_MMR6 : R6MMR6Rel, BEQC_MMR6_ENC, BEQC_MMR6_DESC, ISA_MICROMIPS32R6;
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def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6;
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def BEQC_MMR6 : R6MMR6Rel, BEQC_MMR6_ENC, BEQC_MMR6_DESC, ISA_MICROMIPS32R6,
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DecodeDisambiguates<"POP35GroupBranchMMR6">;
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def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6,
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DecodeDisambiguates<"POP37GroupBranchMMR6">;
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def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
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@ -1557,6 +1624,8 @@ def : MipsInstAlias<"jalrc.hb $rs", (JALRC_HB_MMR6 RA, GPR32Opnd:$rs), 1>,
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ISA_MICROMIPS32R6;
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def : MipsInstAlias<"dvp", (DVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
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def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
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def : MipsInstAlias<"jalrc $rs", (JALRC_MMR6 RA, GPR32Opnd:$rs), 1>,
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ISA_MICROMIPS32R6;
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//===----------------------------------------------------------------------===//
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//
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@ -887,7 +887,8 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
|
||||
def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
|
||||
def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>;
|
||||
}
|
||||
def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
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||||
def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>,
|
||||
ISA_MICROMIPS32_NOT_MIPS32R6;
|
||||
def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
|
||||
|
||||
/// Jump Instructions - Short Delay Slot
|
||||
|
||||
@ -772,8 +772,10 @@ def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
|
||||
def BNEC : R6MMR6Rel, BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
|
||||
def BNEZALC : R6MMR6Rel, BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
|
||||
def BNEZC : R6MMR6Rel, BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
|
||||
def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
|
||||
def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def BNVC : R6MMR6Rel, BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
|
||||
def BOVC : R6MMR6Rel, BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
|
||||
}
|
||||
def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT;
|
||||
@ -854,12 +856,14 @@ def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
|
||||
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;
|
||||
}
|
||||
def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32;
|
||||
}
|
||||
|
||||
def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
|
||||
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
|
||||
}
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// Patterns and Pseudo Instructions
|
||||
|
||||
@ -2006,13 +2006,14 @@ let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
|
||||
0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
|
||||
def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
|
||||
// TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
|
||||
def EXT : MMRel, StdMMR6Rel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1,
|
||||
immZExt5, immZExt5Plus1, MipsExt>,
|
||||
EXT_FM<0>;
|
||||
def INS : MMRel, StdMMR6Rel, InsBase<"ins", GPR32Opnd, uimm5,
|
||||
uimm5_inssize_plus1, MipsIns>,
|
||||
EXT_FM<4>;
|
||||
}
|
||||
// TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
|
||||
def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5,
|
||||
immZExt5Plus1, MipsExt>, EXT_FM<0>;
|
||||
def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1, MipsIns>,
|
||||
EXT_FM<4>;
|
||||
|
||||
/// Move Control Registers From/To CPU Registers
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>,
|
||||
|
||||
@ -319,3 +319,9 @@
|
||||
0x41 0x3f 0x00 0x02 # CHECK: bc1nezc $f31, 4
|
||||
0x41 0x5f 0x00 0x04 # CHECK: bc2eqzc $31, 8
|
||||
0x41 0x7f 0x00 0x04 # CHECK: bc2nezc $31, 8
|
||||
0x01 0x26 0x30 0xec # CHECK: ext $9, $6, 3, 7
|
||||
0x01 0x26 0x48 0xcc # CHECK: ins $9, $6, 3, 7
|
||||
0x00 0x85 0x0f 0x3c # CHECK: jalrc $4, $5
|
||||
0x03 0xe5 0x0f 0x3c # CHECK: jalrc $5
|
||||
0x74 0x44 0x00 0x0c # CHECK: bovc $2, $4, 24
|
||||
0x7c 0x44 0x00 0x0c # CHECK: bnvc $2, $4, 24
|
||||
|
||||
@ -234,3 +234,5 @@
|
||||
bc2nezc $31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
|
||||
bc2nezc $31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
|
||||
bc2nezc $31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
|
||||
jalrc $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
|
||||
jalrc $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
|
||||
|
||||
@ -339,3 +339,11 @@
|
||||
bc1nezc $f31, 4 # CHECK: bc1nezc $f31, 4 # encoding: [0x41,0x3f,0x00,0x02]
|
||||
bc2eqzc $31, 8 # CHECK: bc2eqzc $31, 8 # encoding: [0x41,0x5f,0x00,0x04]
|
||||
bc2nezc $31, 8 # CHECK: bc2nezc $31, 8 # encoding: [0x41,0x7f,0x00,0x04]
|
||||
ins $9, $6, 3, 7 # CHECK: ins $9, $6, 3, 7 # encoding: [0x01,0x26,0x48,0xcc]
|
||||
jalrc $4, $5 # CHECK: jalrc $4, $5 # encoding: [0x00,0x85,0x0f,0x3c]
|
||||
jalrc $5 # CHECK: jalrc $5 # encoding: [0x03,0xe5,0x0f,0x3c]
|
||||
ext $9, $6, 3, 7 # CHECK: ext $9, $6, 3, 7 # encoding: [0x01,0x26,0x30,0xec]
|
||||
bovc $2, $4, 24 # CHECK: bovc $2, $4, 24 # encoding: [0x74,0x44,0x00,0x0c]
|
||||
bovc $4, $2, 24 # CHECK: bovc $4, $2, 24 # encoding: [0x74,0x44,0x00,0x0c]
|
||||
bnvc $2, $4, 24 # CHECK: bnvc $2, $4, 24 # encoding: [0x7c,0x44,0x00,0x0c]
|
||||
bnvc $4, $2, 24 # CHECK: bnvc $4, $2, 24 # encoding: [0x7c,0x44,0x00,0x0c]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user