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[MachineOutliner] Don't outline sequences where x16/x17/nzcv are live across
It isn't safe to outline sequences of instructions where x16/x17/nzcv live across the sequence. This teaches the outliner to check whether or not a specific canidate has x16/x17/nzcv live across it and discard the candidate in the case that that is true. https://bugs.llvm.org/show_bug.cgi?id=37573 https://reviews.llvm.org/D47655 llvm-svn: 335758
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@ -16,7 +16,9 @@
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#ifndef LLVM_MACHINEOUTLINER_H
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#define LLVM_MACHINEOUTLINER_H
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#include "llvm/CodeGen/LiveRegUnits.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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namespace llvm {
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namespace outliner {
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@ -91,6 +93,13 @@ public:
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/// Contains all target-specific information for this \p Candidate.
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TargetCostInfo TCI;
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/// Contains physical register liveness information for the MBB containing
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/// this \p Candidate.
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///
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/// This is optionally used by the target to calculate more fine-grained
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/// cost model information.
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LiveRegUnits LRU;
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/// Return the number of instructions in this Candidate.
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unsigned getLength() const { return Len; }
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@ -120,12 +129,27 @@ public:
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unsigned FunctionIdx)
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: StartIdx(StartIdx), Len(Len), FirstInst(FirstInst), LastInst(LastInst),
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MBB(MBB), FunctionIdx(FunctionIdx) {}
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Candidate() {}
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/// Used to ensure that \p Candidates are outlined in an order that
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/// preserves the start and end indices of other \p Candidates.
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bool operator<(const Candidate &RHS) const {
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return getStartIdx() > RHS.getStartIdx();
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}
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/// Compute the registers that are live across this Candidate.
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/// Used by targets that need this information for cost model calculation.
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/// If a target does not need this information, then this should not be
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/// called.
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void initLRU(const TargetRegisterInfo &TRI) {
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LRU.init(TRI);
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LRU.addLiveOuts(*MBB);
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// Compute liveness from the end of the block up to the beginning of the
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// outlining candidate.
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std::for_each(MBB->rbegin(), (MachineBasicBlock::reverse_iterator)front(),
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[this](MachineInstr &MI) { LRU.stepBackward(MI); });
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}
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};
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/// The information necessary to create an outlined function for some
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@ -65,7 +65,6 @@
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DIBuilder.h"
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#include "llvm/IR/IRBuilder.h"
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@ -19,7 +19,6 @@
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/LiveRegUnits.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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@ -4928,25 +4927,6 @@ enum MachineOutlinerMBBFlags {
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HasCalls = 0x4
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};
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bool AArch64InstrInfo::canOutlineWithoutLRSave(
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MachineBasicBlock::iterator &CallInsertionPt) const {
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// Was LR saved in the function containing this basic block?
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MachineBasicBlock &MBB = *(CallInsertionPt->getParent());
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LiveRegUnits LRU(getRegisterInfo());
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LRU.addLiveOuts(MBB);
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// Get liveness information from the end of the block to the end of the
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// prospective outlined region.
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std::for_each(MBB.rbegin(),
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(MachineBasicBlock::reverse_iterator)CallInsertionPt,
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[&LRU](MachineInstr &MI) { LRU.stepBackward(MI); });
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// If the link register is available at this point, then we can safely outline
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// the region without saving/restoring LR. Otherwise, we must emit a save and
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// restore.
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return LRU.available(AArch64::LR);
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}
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outliner::TargetCostInfo
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AArch64InstrInfo::getOutlininingCandidateInfo(
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std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
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@ -4961,8 +4941,38 @@ AArch64InstrInfo::getOutlininingCandidateInfo(
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unsigned NumBytesForCall = 12;
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unsigned NumBytesToCreateFrame = 4;
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auto DoesntNeedLRSave =
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[this](outliner::Candidate &I) {return canOutlineWithoutLRSave(I.back());};
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// Compute liveness information for each candidate.
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const TargetRegisterInfo &TRI = getRegisterInfo();
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std::for_each(RepeatedSequenceLocs.begin(), RepeatedSequenceLocs.end(),
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[&TRI](outliner::Candidate &C) { C.initLRU(TRI); });
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// According to the AArch64 Procedure Call Standard, the following are
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// undefined on entry/exit from a function call:
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//
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// * Registers x16, x17, (and thus w16, w17)
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// * Condition codes (and thus the NZCV register)
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//
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// Because if this, we can't outline any sequence of instructions where
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// one
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// of these registers is live into/across it. Thus, we need to delete
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// those
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// candidates.
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auto CantGuaranteeValueAcrossCall = [](outliner::Candidate &C) {
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LiveRegUnits LRU = C.LRU;
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return (!LRU.available(AArch64::W16) || !LRU.available(AArch64::W17) ||
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!LRU.available(AArch64::NZCV));
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};
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// Erase every candidate that violates the restrictions above. (It could be
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// true that we have viable candidates, so it's not worth bailing out in
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// the case that, say, 1 out of 20 candidates violate the restructions.)
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RepeatedSequenceLocs.erase(std::remove_if(RepeatedSequenceLocs.begin(),
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RepeatedSequenceLocs.end(),
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CantGuaranteeValueAcrossCall),
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RepeatedSequenceLocs.end());
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// At this point, we have only "safe" candidates to outline. Figure out
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// frame + call instruction information.
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unsigned LastInstrOpcode = RepeatedSequenceLocs[0].back()->getOpcode();
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@ -4983,8 +4993,15 @@ AArch64InstrInfo::getOutlininingCandidateInfo(
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NumBytesToCreateFrame = 0;
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}
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else if (std::all_of(RepeatedSequenceLocs.begin(), RepeatedSequenceLocs.end(),
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DoesntNeedLRSave)) {
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// Make sure that LR isn't live on entry to this candidate. The only
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// instructions that use LR that could possibly appear in a repeated sequence
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// are calls. Therefore, we only have to check and see if LR is dead on entry
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// to (or exit from) some candidate.
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else if (std::all_of(RepeatedSequenceLocs.begin(),
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RepeatedSequenceLocs.end(),
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[](outliner::Candidate &C) {
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return C.LRU.available(AArch64::LR);
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})) {
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CallID = MachineOutlinerNoLRSave;
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FrameID = MachineOutlinerNoLRSave;
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NumBytesForCall = 4;
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@ -238,9 +238,6 @@ public:
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/// AArch64 supports the MachineOutliner.
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bool useMachineOutliner() const override { return true; }
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bool
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canOutlineWithoutLRSave(MachineBasicBlock::iterator &CallInsertionPt) const;
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bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
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bool OutlineFromLinkOnceODRs) const override;
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outliner::TargetCostInfo getOutlininingCandidateInfo(
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183
test/CodeGen/AArch64/machine-outliner-bad-register.mir
Normal file
183
test/CodeGen/AArch64/machine-outliner-bad-register.mir
Normal file
@ -0,0 +1,183 @@
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# RUN: llc -mtriple=aarch64--- -run-pass=machine-outliner \
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# RUN: -verify-machineinstrs %s -o - | FileCheck %s
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# Ensure that we don't outline from regions where x16, x17, or nzcv are live
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# across the outlining candidate. These values are allowed to be clobbered by,
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# say, the linker, in the presence of function calls. Thus, we can't outline
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# these, since the insertion of the outlined call could change the values of
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# these registers.
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--- |
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; No problematic register appears at all. Safe for outlining.
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define void @reg_never_defined() #0 { ret void }
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; A problematic register is live, but after the candidate. Safe for outlining.
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define void @reg_defined_after_candidate() #0 { ret void }
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; A problematic register is live before the candidate, but killed before
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; entry to the candidate. Safe for outlining.
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define void @reg_killed_before_candidate() #0 { ret void }
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; Ensure that we never outline when any of the problematic registers we care
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; about are defined across the outlining candidate.
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define void @x16_live() #0 { ret void }
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define void @x17_live() #0 { ret void }
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define void @nzcv_live() #0 { ret void }
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; Test a combination of the above behaviours.
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; [candidate] (1)
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; - define a bad register -
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; [candidate] (2)
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; - kill the bad register -
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; [candidate] (3)
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;
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; (1) and (3) should be outlined, while (2) should not be outlined.
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define void @multiple_ranges() #0 { ret void }
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attributes #0 = { noredzone }
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...
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---
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# There should be two calls to outlined functions here, since we haven't tripped
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# any of the cases above.
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name: reg_never_defined
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: bb.0:
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; CHECK: BL
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liveins: $w8, $wzr
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$w8 = ORRWri $wzr, 1
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$w8 = ORRWri $wzr, 2
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$w8 = ORRWri $wzr, 3
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$w8 = ORRWri $wzr, 4
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bb.1:
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; CHECK-LABEL: bb.1:
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; CHECK: BL
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liveins: $w8, $wzr
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$w8 = ORRWri $wzr, 1
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$w8 = ORRWri $wzr, 2
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$w8 = ORRWri $wzr, 3
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$w8 = ORRWri $wzr, 4
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bb.2:
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RET undef $lr
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...
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---
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name: reg_defined_after_candidate
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: bb.0:
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; CHECK: BL
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; CHECK-NEXT: $x16 = ORRXri $x8, 5, implicit-def $x16, implicit-def $w16
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liveins: $w8, $wzr
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$w8 = ORRWri $wzr, 1
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$w8 = ORRWri $wzr, 2
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$w8 = ORRWri $wzr, 3
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$w8 = ORRWri $wzr, 4
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$x16 = ORRXri $x8, 5, implicit-def $x16, implicit-def $w16
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$w8 = ORRWri $w16, 5
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RET undef $lr
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...
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---
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name: reg_killed_before_candidate
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: bb.0:
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; CHECK: BL
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liveins: $w8, $wzr, $x16
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dead $x16 = ORRXri $x8, 6
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$w8 = ORRWri $wzr, 1
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$w8 = ORRWri $wzr, 2
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$w8 = ORRWri $wzr, 3
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$w8 = ORRWri $wzr, 4
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RET undef $lr
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...
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---
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name: x16_live
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: bb.0:
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; CHECK-NOT: BL
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liveins: $w8, $wzr, $x16
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$w8 = ORRWri $wzr, 1
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$w8 = ORRWri $wzr, 2
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$w8 = ORRWri $wzr, 3
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$w8 = ORRWri $wzr, 4
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bb.1:
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liveins: $x16
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RET undef $lr
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...
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---
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name: x17_live
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: bb.0:
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; CHECK-NOT: BL
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liveins: $w8, $wzr, $x17
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$w8 = ORRWri $wzr, 1
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$w8 = ORRWri $wzr, 2
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$w8 = ORRWri $wzr, 3
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$w8 = ORRWri $wzr, 4
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$w8 = ORRWri $w17, 5
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RET undef $lr
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...
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---
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name: nzcv_live
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w8, $wzr, $nzcv
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; CHECK-LABEL: bb.0:
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; CHECK-NOT: BL
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$w8 = ORRWri $wzr, 1
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$w8 = ORRWri $wzr, 2
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$w8 = ORRWri $wzr, 3
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$w8 = ORRWri $wzr, 4
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bb.1:
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liveins: $nzcv
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RET undef $lr
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...
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---
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name: multiple_ranges
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: bb.0:
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; CHECK: BL
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liveins: $w8, $wzr
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$w8 = ORRWri $wzr, 1
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$w8 = ORRWri $wzr, 2
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$w8 = ORRWri $wzr, 3
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$w8 = ORRWri $wzr, 4
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$x16 = ORRXri $x8, 5, implicit-def $x16
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bb.1:
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; CHECK-LABEL: bb.1:
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; CHECK-NOT: BL
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liveins: $w8, $x16
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$w8 = ORRWri $wzr, 1
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$w8 = ORRWri $wzr, 2
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$w8 = ORRWri $wzr, 3
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$w8 = ORRWri $wzr, 4
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bb.2:
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; CHECK-LABEL: bb.2:
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; CHECK: BL
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liveins: $w8, $x16
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dead $x16 = ORRXri $x8, 0
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$w8 = ORRWri $wzr, 1
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$w8 = ORRWri $wzr, 2
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$w8 = ORRWri $wzr, 3
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$w8 = ORRWri $wzr, 4
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bb.3:
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liveins: $w8
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RET undef $lr
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...
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---
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