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Add new intrinsics for Neon vldN_lane and vstN_lane operations.
llvm-svn: 79716
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16535e6ae7
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@ -326,6 +326,23 @@ let TargetPrefix = "arm" in {
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LLVMMatchType<0>, LLVMMatchType<0>],
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[llvm_ptr_ty], [IntrReadArgMem]>;
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// Vector load N-element structure to one lane.
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def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
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[llvm_ptr_ty, LLVMMatchType<0>,
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LLVMMatchType<0>, llvm_i32_ty],
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[IntrReadArgMem]>;
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def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
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LLVMMatchType<0>],
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[llvm_ptr_ty, LLVMMatchType<0>,
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LLVMMatchType<0>, LLVMMatchType<0>,
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llvm_i32_ty], [IntrReadArgMem]>;
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def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
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LLVMMatchType<0>, LLVMMatchType<0>],
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[llvm_ptr_ty, LLVMMatchType<0>,
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LLVMMatchType<0>, LLVMMatchType<0>,
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LLVMMatchType<0>, llvm_i32_ty],
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[IntrReadArgMem]>;
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// Interleaving vector stores from N-element structures.
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def int_arm_neon_vst1 : Intrinsic<[llvm_void_ty],
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[llvm_ptr_ty, llvm_anyvector_ty],
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@ -341,4 +358,19 @@ let TargetPrefix = "arm" in {
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[llvm_ptr_ty, llvm_anyvector_ty,
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LLVMMatchType<0>, LLVMMatchType<0>,
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LLVMMatchType<0>], [IntrWriteArgMem]>;
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// Vector store N-element structure from one lane.
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def int_arm_neon_vst2lane : Intrinsic<[llvm_void_ty],
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[llvm_ptr_ty, llvm_anyvector_ty,
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LLVMMatchType<0>, llvm_i32_ty],
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[IntrWriteArgMem]>;
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def int_arm_neon_vst3lane : Intrinsic<[llvm_void_ty],
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[llvm_ptr_ty, llvm_anyvector_ty,
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LLVMMatchType<0>, LLVMMatchType<0>,
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llvm_i32_ty], [IntrWriteArgMem]>;
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def int_arm_neon_vst4lane : Intrinsic<[llvm_void_ty],
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[llvm_ptr_ty, llvm_anyvector_ty,
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LLVMMatchType<0>, LLVMMatchType<0>,
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LLVMMatchType<0>, llvm_i32_ty],
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[IntrWriteArgMem]>;
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}
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