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Revert "AMDGPU: Remove unused control flow intrinsic"
llvm-svn: 274978
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e11a36897f
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@ -37,6 +37,7 @@ typedef SmallVector<StackEntry, 16> StackVector;
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// Intrinsic names the control flow is annotated with
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static const char *const IfIntrinsic = "llvm.amdgcn.if";
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static const char *const ElseIntrinsic = "llvm.amdgcn.else";
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static const char *const BreakIntrinsic = "llvm.amdgcn.break";
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static const char *const IfBreakIntrinsic = "llvm.amdgcn.if.break";
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static const char *const ElseBreakIntrinsic = "llvm.amdgcn.else.break";
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static const char *const LoopIntrinsic = "llvm.amdgcn.loop";
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@ -145,6 +146,9 @@ bool SIAnnotateControlFlow::doInitialization(Module &M) {
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Else = M.getOrInsertFunction(
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ElseIntrinsic, ReturnStruct, Int64, (Type *)nullptr);
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Break = M.getOrInsertFunction(
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BreakIntrinsic, Int64, Int64, (Type *)nullptr);
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IfBreak = M.getOrInsertFunction(
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IfBreakIntrinsic, Int64, Boolean, Int64, (Type *)nullptr);
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@ -72,6 +72,7 @@ bool SIFixControlFlowLiveIntervals::runOnMachineFunction(MachineFunction &MF) {
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switch (MI.getOpcode()) {
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case AMDGPU::SI_IF:
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case AMDGPU::SI_ELSE:
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case AMDGPU::SI_BREAK:
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case AMDGPU::SI_IF_BREAK:
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case AMDGPU::SI_ELSE_BREAK:
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case AMDGPU::SI_END_CF: {
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@ -324,6 +324,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
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assert(DefInstr);
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switch(DefInstr->getOpcode()) {
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case AMDGPU::SI_BREAK:
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case AMDGPU::SI_IF_BREAK:
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case AMDGPU::SI_ELSE_BREAK:
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// If we see a PHI instruction that defines an SGPR, then that PHI
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@ -1261,6 +1261,7 @@ bool SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
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default: return false;
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case AMDGPUIntrinsic::amdgcn_if:
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case AMDGPUIntrinsic::amdgcn_else:
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case AMDGPUIntrinsic::amdgcn_break:
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case AMDGPUIntrinsic::amdgcn_if_break:
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case AMDGPUIntrinsic::amdgcn_else_break:
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case AMDGPUIntrinsic::amdgcn_loop:
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@ -1958,6 +1958,11 @@ def SI_LOOP : InstSI <
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} // End isBranch = 1, isTerminator = 1
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def SI_BREAK : InstSI <
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(outs SReg_64:$dst), (ins SReg_64:$src), "",
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[(set i64:$dst, (int_amdgcn_break i64:$src))]
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>;
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def SI_IF_BREAK : InstSI <
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(outs SReg_64:$dst), (ins SReg_64:$vcc, SReg_64:$src), "",
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[(set i64:$dst, (int_amdgcn_if_break i1:$vcc, i64:$src))]
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@ -181,6 +181,7 @@ let TargetPrefix = "amdgcn", isTarget = 1 in {
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def int_amdgcn_if : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_empty_ty], []>;
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def int_amdgcn_else : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_empty_ty], []>;
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def int_amdgcn_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], []>;
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def int_amdgcn_if_break : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_i64_ty], []>;
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def int_amdgcn_else_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], []>;
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def int_amdgcn_loop : Intrinsic<[], [llvm_i64_ty, llvm_empty_ty], []>;
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@ -80,6 +80,7 @@ private:
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void If(MachineInstr &MI);
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void Else(MachineInstr &MI, bool ExecModified);
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void Break(MachineInstr &MI);
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void IfBreak(MachineInstr &MI);
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void ElseBreak(MachineInstr &MI);
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void Loop(MachineInstr &MI);
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@ -276,6 +277,20 @@ void SILowerControlFlow::Else(MachineInstr &MI, bool ExecModified) {
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MI.eraseFromParent();
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}
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void SILowerControlFlow::Break(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Dst = MI.getOperand(0).getReg();
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unsigned Src = MI.getOperand(1).getReg();
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
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.addReg(AMDGPU::EXEC)
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.addReg(Src);
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MI.eraseFromParent();
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}
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void SILowerControlFlow::IfBreak(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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@ -661,6 +676,10 @@ bool SILowerControlFlow::runOnMachineFunction(MachineFunction &MF) {
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Else(MI, ExecModified);
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break;
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case AMDGPU::SI_BREAK:
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Break(MI);
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break;
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case AMDGPU::SI_IF_BREAK:
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IfBreak(MI);
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break;
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