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Add backend name to Target to enable runtime info to be fed back into TableGen

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Summary:
Make it possible to feed runtime information back to tablegen to enable
profile-guided tablegen-eration, detection of untested tablegen definitions, etc.

Being a cross-compiler by nature, LLVM will potentially collect data for multiple
architectures (e.g. when running 'ninja check'). We therefore need a way for
TableGen to figure out what data applies to the backend it is generating at the
time. This patch achieves that by including the name of the 'def X : Target ...'
for the backend in the TargetRegistry.

Reviewers: qcolombet

Reviewed By: qcolombet

Subscribers: jholewinski, arsenm, jyknight, aditya_nandakumar, sdardis, nemanjai, ab, nhaehnle, t.p.northover, javed.absar, qcolombet, llvm-commits, fedor.sergeev

Differential Revision: https://reviews.llvm.org/D39742

llvm-svn: 318352
This commit is contained in:
Daniel Sanders 2017-11-15 23:55:44 +00:00
parent ee25897122
commit 6503157726
16 changed files with 58 additions and 40 deletions
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18
include/llvm/Support/TargetRegistry.h
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@ -187,6 +187,10 @@ private:
/// ShortDesc - A short description of the target.
const char *ShortDesc;
/// BackendName - The name of the backend implementation. This must match the
/// name of the 'def X : Target ...' in TableGen.
const char *BackendName;
/// HasJIT - Whether this target supports the JIT.
bool HasJIT;
@ -279,6 +283,9 @@ public:
/// getShortDescription - Get a short description of the target.
const char *getShortDescription() const { return ShortDesc; }
/// getBackendName - Get the backend name.
const char *getBackendName() const { return BackendName; }
/// @}
/// @name Feature Predicates
/// @{
@ -645,10 +652,15 @@ struct TargetRegistry {
/// @param Name - The target name. This should be a static string.
/// @param ShortDesc - A short target description. This should be a static
/// string.
/// @param BackendName - The name of the backend. This should be a static
/// string that is the same for all targets that share a backend
/// implementation and must match the name used in the 'def X : Target ...' in
/// TableGen.
/// @param ArchMatchFn - The arch match checking function for this target.
/// @param HasJIT - Whether the target supports JIT code
/// generation.
static void RegisterTarget(Target &T, const char *Name, const char *ShortDesc,
const char *BackendName,
Target::ArchMatchFnTy ArchMatchFn,
bool HasJIT = false);
@ -883,8 +895,10 @@ struct TargetRegistry {
template <Triple::ArchType TargetArchType = Triple::UnknownArch,
bool HasJIT = false>
struct RegisterTarget {
RegisterTarget(Target &T, const char *Name, const char *Desc) {
TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch, HasJIT);
RegisterTarget(Target &T, const char *Name, const char *Desc,
const char *BackendName) {
TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
HasJIT);
}
static bool getArchMatch(Triple::ArchType Arch) {

5
lib/Support/TargetRegistry.cpp
View File

@ -86,9 +86,9 @@ const Target *TargetRegistry::lookupTarget(const std::string &TT,
return &*I;
}
void TargetRegistry::RegisterTarget(Target &T,
const char *Name,
void TargetRegistry::RegisterTarget(Target &T, const char *Name,
const char *ShortDesc,
const char *BackendName,
Target::ArchMatchFnTy ArchMatchFn,
bool HasJIT) {
assert(Name && ShortDesc && ArchMatchFn &&
@ -105,6 +105,7 @@ void TargetRegistry::RegisterTarget(Target &T,
T.Name = Name;
T.ShortDesc = ShortDesc;
T.BackendName = BackendName;
T.ArchMatchFn = ArchMatchFn;
T.HasJIT = HasJIT;
}

6
lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
View File

@ -29,11 +29,11 @@ extern "C" void LLVMInitializeAArch64TargetInfo() {
// Now register the "arm64" name for use with "-march". We don't want it to
// take possession of the Triple::aarch64 tag though.
TargetRegistry::RegisterTarget(getTheARM64Target(), "arm64",
"ARM64 (little endian)",
"ARM64 (little endian)", "AArch64",
[](Triple::ArchType) { return false; }, true);
RegisterTarget<Triple::aarch64, /*HasJIT=*/true> Z(
getTheAArch64leTarget(), "aarch64", "AArch64 (little endian)");
getTheAArch64leTarget(), "aarch64", "AArch64 (little endian)", "AArch64");
RegisterTarget<Triple::aarch64_be, /*HasJIT=*/true> W(
getTheAArch64beTarget(), "aarch64_be", "AArch64 (big endian)");
getTheAArch64beTarget(), "aarch64_be", "AArch64 (big endian)", "AArch64");
}

4
lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
View File

@ -31,7 +31,7 @@ Target &llvm::getTheGCNTarget() {
/// \brief Extern function to initialize the targets for the AMDGPU backend
extern "C" void LLVMInitializeAMDGPUTargetInfo() {
RegisterTarget<Triple::r600, false> R600(getTheAMDGPUTarget(), "r600",
"AMD GPUs HD2XXX-HD6XXX");
"AMD GPUs HD2XXX-HD6XXX", "AMDGPU");
RegisterTarget<Triple::amdgcn, false> GCN(getTheGCNTarget(), "amdgcn",
"AMD GCN GPUs");
"AMD GCN GPUs", "AMDGPU");
}

8
lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp
View File

@ -30,12 +30,12 @@ Target &llvm::getTheThumbBETarget() {
extern "C" void LLVMInitializeARMTargetInfo() {
RegisterTarget<Triple::arm, /*HasJIT=*/true> X(getTheARMLETarget(), "arm",
"ARM");
"ARM", "ARM");
RegisterTarget<Triple::armeb, /*HasJIT=*/true> Y(getTheARMBETarget(), "armeb",
"ARM (big endian)");
"ARM (big endian)", "ARM");
RegisterTarget<Triple::thumb, /*HasJIT=*/true> A(getTheThumbLETarget(),
"thumb", "Thumb");
"thumb", "Thumb", "ARM");
RegisterTarget<Triple::thumbeb, /*HasJIT=*/true> B(
getTheThumbBETarget(), "thumbeb", "Thumb (big endian)");
getTheThumbBETarget(), "thumbeb", "Thumb (big endian)", "ARM");
}

9
lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp
View File

@ -28,9 +28,10 @@ Target &getTheBPFTarget() {
extern "C" void LLVMInitializeBPFTargetInfo() {
TargetRegistry::RegisterTarget(getTheBPFTarget(), "bpf", "BPF (host endian)",
[](Triple::ArchType) { return false; }, true);
RegisterTarget<Triple::bpfel, /*HasJIT=*/true> X(getTheBPFleTarget(), "bpfel",
"BPF (little endian)");
"BPF", [](Triple::ArchType) { return false; },
true);
RegisterTarget<Triple::bpfel, /*HasJIT=*/true> X(
getTheBPFleTarget(), "bpfel", "BPF (little endian)", "BPF");
RegisterTarget<Triple::bpfeb, /*HasJIT=*/true> Y(getTheBPFbeTarget(), "bpfeb",
"BPF (big endian)");
"BPF (big endian)", "BPF");
}

4
lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
View File

@ -18,6 +18,6 @@ Target &llvm::getTheHexagonTarget() {
}
extern "C" void LLVMInitializeHexagonTargetInfo() {
RegisterTarget<Triple::hexagon, /*HasJIT=*/false> X(getTheHexagonTarget(),
"hexagon", "Hexagon");
RegisterTarget<Triple::hexagon, /*HasJIT=*/false> X(
getTheHexagonTarget(), "hexagon", "Hexagon", "Hexagon");
}

3
lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp
View File

@ -21,5 +21,6 @@ Target &getTheLanaiTarget() {
} // namespace llvm
extern "C" void LLVMInitializeLanaiTargetInfo() {
RegisterTarget<Triple::lanai> X(getTheLanaiTarget(), "lanai", "Lanai");
RegisterTarget<Triple::lanai> X(getTheLanaiTarget(), "lanai", "Lanai",
"Lanai");
}

2
lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp
View File

@ -19,5 +19,5 @@ Target &llvm::getTheMSP430Target() {
extern "C" void LLVMInitializeMSP430TargetInfo() {
RegisterTarget<Triple::msp430> X(getTheMSP430Target(), "msp430",
"MSP430 [experimental]");
"MSP430 [experimental]", "MSP430");
}

8
lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
View File

@ -32,17 +32,17 @@ Target &llvm::getTheMips64elTarget() {
extern "C" void LLVMInitializeMipsTargetInfo() {
RegisterTarget<Triple::mips,
/*HasJIT=*/true>
X(getTheMipsTarget(), "mips", "Mips");
X(getTheMipsTarget(), "mips", "Mips", "Mips");
RegisterTarget<Triple::mipsel,
/*HasJIT=*/true>
Y(getTheMipselTarget(), "mipsel", "Mipsel");
Y(getTheMipselTarget(), "mipsel", "Mipsel", "Mips");
RegisterTarget<Triple::mips64,
/*HasJIT=*/true>
A(getTheMips64Target(), "mips64", "Mips64 [experimental]");
A(getTheMips64Target(), "mips64", "Mips64 [experimental]", "Mips");
RegisterTarget<Triple::mips64el,
/*HasJIT=*/true>
B(getTheMips64elTarget(), "mips64el", "Mips64el [experimental]");
B(getTheMips64elTarget(), "mips64el", "Mips64el [experimental]", "Mips");
}

4
lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp
View File

@ -23,7 +23,7 @@ Target &llvm::getTheNVPTXTarget64() {
extern "C" void LLVMInitializeNVPTXTargetInfo() {
RegisterTarget<Triple::nvptx> X(getTheNVPTXTarget32(), "nvptx",
"NVIDIA PTX 32-bit");
"NVIDIA PTX 32-bit", "NVPTX");
RegisterTarget<Triple::nvptx64> Y(getTheNVPTXTarget64(), "nvptx64",
"NVIDIA PTX 64-bit");
"NVIDIA PTX 64-bit", "NVPTX");
}

6
lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp
View File

@ -27,11 +27,11 @@ Target &llvm::getThePPC64LETarget() {
extern "C" void LLVMInitializePowerPCTargetInfo() {
RegisterTarget<Triple::ppc, /*HasJIT=*/true> X(getThePPC32Target(), "ppc32",
"PowerPC 32");
"PowerPC 32", "PPC");
RegisterTarget<Triple::ppc64, /*HasJIT=*/true> Y(getThePPC64Target(), "ppc64",
"PowerPC 64");
"PowerPC 64", "PPC");
RegisterTarget<Triple::ppc64le, /*HasJIT=*/true> Z(
getThePPC64LETarget(), "ppc64le", "PowerPC 64 LE");
getThePPC64LETarget(), "ppc64le", "PowerPC 64 LE", "PPC");
}

10
lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp
View File

@ -27,9 +27,9 @@ Target &llvm::getTheSparcelTarget() {
extern "C" void LLVMInitializeSparcTargetInfo() {
RegisterTarget<Triple::sparc, /*HasJIT=*/true> X(getTheSparcTarget(), "sparc",
"Sparc");
RegisterTarget<Triple::sparcv9, /*HasJIT=*/true> Y(getTheSparcV9Target(),
"sparcv9", "Sparc V9");
RegisterTarget<Triple::sparcel, /*HasJIT=*/true> Z(getTheSparcelTarget(),
"sparcel", "Sparc LE");
"Sparc", "Sparc");
RegisterTarget<Triple::sparcv9, /*HasJIT=*/true> Y(
getTheSparcV9Target(), "sparcv9", "Sparc V9", "Sparc");
RegisterTarget<Triple::sparcel, /*HasJIT=*/true> Z(
getTheSparcelTarget(), "sparcel", "Sparc LE", "Sparc");
}

4
lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp
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@ -18,6 +18,6 @@ Target &llvm::getTheSystemZTarget() {
}
extern "C" void LLVMInitializeSystemZTargetInfo() {
RegisterTarget<Triple::systemz, /*HasJIT=*/true> X(getTheSystemZTarget(),
"systemz", "SystemZ");
RegisterTarget<Triple::systemz, /*HasJIT=*/true> X(
getTheSystemZTarget(), "systemz", "SystemZ", "SystemZ");
}

4
lib/Target/X86/TargetInfo/X86TargetInfo.cpp
View File

@ -22,8 +22,8 @@ Target &llvm::getTheX86_64Target() {
extern "C" void LLVMInitializeX86TargetInfo() {
RegisterTarget<Triple::x86, /*HasJIT=*/true> X(
getTheX86_32Target(), "x86", "32-bit X86: Pentium-Pro and above");
getTheX86_32Target(), "x86", "32-bit X86: Pentium-Pro and above", "X86");
RegisterTarget<Triple::x86_64, /*HasJIT=*/true> Y(
getTheX86_64Target(), "x86-64", "64-bit X86: EM64T and AMD64");
getTheX86_64Target(), "x86-64", "64-bit X86: EM64T and AMD64", "X86");
}

3
lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp
View File

@ -18,5 +18,6 @@ Target &llvm::getTheXCoreTarget() {
}
extern "C" void LLVMInitializeXCoreTargetInfo() {
RegisterTarget<Triple::xcore> X(getTheXCoreTarget(), "xcore", "XCore");
RegisterTarget<Triple::xcore> X(getTheXCoreTarget(), "xcore", "XCore",
"XCore");
}