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Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.

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llvm-svn: 140370
This commit is contained in:
Craig Topper 2011-09-23 06:57:25 +00:00
parent 102afe6879
commit 655f8a01e6
5 changed files with 23 additions and 13 deletions
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11
test/MC/Disassembler/X86/intel-syntax.txt
View File

@ -12,14 +12,11 @@
# CHECK: movsq
0x48 0xa5
# CHECK: pop DS
0x1f
# CHECK: pop FS
0x0f 0xa1
# CHECK: pop ES
0x07
# CHECK: pop SS
0x17
# CHECK: pop GS
0x0f 0xa9
# CHECK: in AL, DX
0xec

6
utils/TableGen/X86DisassemblerTables.cpp
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@ -642,12 +642,16 @@ void DisassemblerTables::setTableFields(OpcodeType type,
InstructionContext insnContext,
uint8_t opcode,
const ModRMFilter &filter,
InstrUID uid) {
InstrUID uid,
bool is32bit) {
unsigned index;
ContextDecision &decision = *Tables[type];
for (index = 0; index < IC_max; ++index) {
if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
continue;
if (inheritsFrom((InstructionContext)index,
InstructionSpecifiers[uid].insnContext))
setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],

4
utils/TableGen/X86DisassemblerTables.h
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@ -260,11 +260,13 @@ public:
/// @param filter - The ModRMFilter that decides which ModR/M byte values
/// correspond to the desired instruction.
/// @param uid - The unique ID of the instruction.
/// @param is32bit - Instructon is only 32-bit
void setTableFields(OpcodeType type,
InstructionContext insnContext,
uint8_t opcode,
const ModRMFilter &filter,
InstrUID uid);
InstrUID uid,
bool is32bit);
/// specForUID - Returns the instruction specifier for a given unique
/// instruction ID. Used when resolving collisions.

11
utils/TableGen/X86RecognizableInstr.cpp
View File

@ -231,10 +231,15 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
// Check for 64-bit inst which does not require REX
Is32Bit = false;
Is64Bit = false;
// FIXME: Is there some better way to check for In64BitMode?
std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
if (Predicates[i]->getName().find("32Bit") != Name.npos) {
Is32Bit = true;
break;
}
if (Predicates[i]->getName().find("64Bit") != Name.npos) {
Is64Bit = true;
break;
@ -947,7 +952,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
insnContext(),
currentOpcode,
*filter,
UID);
UID, Is32Bit);
Spec->modifierType = MODIFIER_OPCODE;
Spec->modifierBase = opcodeToSet;
@ -957,14 +962,14 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
insnContext(),
opcodeToSet,
*filter,
UID);
UID, Is32Bit);
}
} else {
tables.setTableFields(opcodeType,
insnContext(),
opcodeToSet,
*filter,
UID);
UID, Is32Bit);
Spec->modifierType = MODIFIER_NONE;
Spec->modifierBase = opcodeToSet;

4
utils/TableGen/X86RecognizableInstr.h
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@ -64,8 +64,10 @@ private:
bool HasLockPrefix;
/// The isCodeGenOnly filed from the record
bool IsCodeGenOnly;
// Whether the instruction has the predicate "Mode64Bit"
// Whether the instruction has the predicate "In64BitMode"
bool Is64Bit;
// Whether the instruction has the predicate "In32BitMode"
bool Is32Bit;
/// The instruction name as listed in the tables
std::string Name;