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On DataLayout, omit the default of p:64:64:64.

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llvm-svn: 197397
This commit is contained in:
Rafael Espindola 2013-12-16 17:15:29 +00:00
parent fef994be39
commit 65c80ee4a2
8 changed files with 11 additions and 23 deletions
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2
lib/Target/AArch64/AArch64TargetMachine.cpp
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@ -34,7 +34,7 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS),
InstrInfo(Subtarget),
DL("e-p:64:64-i64:64:64-i128:128:128-s:32:32-n32:64-S128"),
DL("e-i64:64:64-i128:128:128-s:32:32-n32:64-S128"),
TLInfo(*this),
TSInfo(*this),
FrameLowering(Subtarget) {

6
lib/Target/Mips/MipsTargetMachine.cpp
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@ -54,10 +54,8 @@ static std::string computeDataLayout(const MipsSubtarget &ST) {
else
Ret += "E";
// Pointers are 64 or 32 bit depending on the ABI.
if (ST.isABI_N64())
Ret += "-p:64:64:64";
else
// Pointers are 32 bit on some ABIs.
if (!ST.isABI_N64())
Ret += "-p:32:32:32";
// 8 and 16 bit integers only need no have natural alignment, but try to

4
lib/Target/NVPTX/NVPTXTargetMachine.cpp
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@ -66,9 +66,7 @@ extern "C" void LLVMInitializeNVPTXTarget() {
static std::string computeDataLayout(const NVPTXSubtarget &ST) {
std::string Ret = "e";
if (ST.is64Bit())
Ret += "-p:64:64:64";
else
if (!ST.is64Bit())
Ret += "-p:32:32:32";
Ret += "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"

6
lib/Target/PowerPC/PPCTargetMachine.cpp
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@ -38,10 +38,8 @@ static std::string getDataLayoutString(const PPCSubtarget &ST) {
// PPC is big endian.
std::string Ret = "E";
// PPC64 has 64 bit pointers, PPC32 has 32 bit pointers.
if (ST.isPPC64())
Ret += "-p:64:64";
else
// PPC32 has 32 bit pointers.
if (!ST.isPPC64())
Ret += "-p:32:32";
// Note, the alignment values for f64 and i64 on ppc64 in Darwin

4
lib/Target/R600/AMDGPUTargetMachine.cpp
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@ -61,9 +61,7 @@ static std::string computeDataLayout(const AMDGPUSubtarget &ST) {
if (ST.hasHWFP64())
DataLayout.append("-f64:64:64");
if (ST.is64bit())
DataLayout.append("-p:64:64:64");
else
if (!ST.is64bit())
DataLayout.append("-p:32:32:32");
if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)

6
lib/Target/Sparc/SparcTargetMachine.cpp
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@ -27,10 +27,8 @@ static std::string computeDataLayout(const SparcSubtarget &ST) {
// Sparc is big endian.
std::string Ret = "E";
// V9 has 64 bit pointers, others have 32bit pointers.
if (ST.is64Bit())
Ret += "-p:64:64:64";
else
// Some ABIs have 32bit pointers.
if (!ST.is64Bit())
Ret += "-p:32:32:32";
// Alignments for 64 bit integers.

2
lib/Target/SystemZ/SystemZTargetMachine.cpp
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@ -30,7 +30,7 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, StringRef TT,
// Make sure that global data has at least 16 bits of alignment by default,
// so that we can refer to it using LARL. We don't have any special
// requirements for stack variables though.
DL("E-p:64:64:64-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"),
DL("E-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"),
InstrInfo(*this), TLInfo(*this), TSInfo(*this),
FrameLowering(*this, Subtarget) {
initAsmInfo();

4
lib/Target/X86/X86TargetMachine.cpp
View File

@ -34,11 +34,9 @@ static std::string computeDataLayout(const X86Subtarget &ST) {
// X86 is little endian
std::string Ret = "e";
// X86 and x32 have 32 bit pointers, x86-64 has 64 bit pointers
// X86 and x32 have 32 bit pointers.
if (ST.isTarget64BitILP32() || !ST.is64Bit())
Ret += "-p:32:32";
else
Ret += "-p:64:64";
// Objects on the stack ore aligned to 64 bits.
// FIXME: of any size?