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Fix bugs in lowering of FCOPYSIGN nodes.
- FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
This commit is contained in:
Akira Hatanaka
parent
8327980405
commit
6636922675
@ -1756,66 +1756,105 @@ SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
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MachinePointerInfo(SV), false, false, 0);
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}
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// Called if the size of integer registers is large enough to hold the whole
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// floating point number.
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static SDValue LowerFCOPYSIGNLargeIntReg(SDValue Op, SelectionDAG &DAG) {
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// FIXME: Use ext/ins instructions if target architecture is Mips32r2.
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EVT ValTy = Op.getValueType();
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EVT IntValTy = MVT::getIntegerVT(ValTy.getSizeInBits());
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uint64_t Mask = (uint64_t)1 << (ValTy.getSizeInBits() - 1);
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DebugLoc dl = Op.getDebugLoc();
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SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntValTy, Op.getOperand(0));
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SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntValTy, Op.getOperand(1));
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SDValue And0 = DAG.getNode(ISD::AND, dl, IntValTy, Op0,
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DAG.getConstant(Mask - 1, IntValTy));
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SDValue And1 = DAG.getNode(ISD::AND, dl, IntValTy, Op1,
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DAG.getConstant(Mask, IntValTy));
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SDValue Result = DAG.getNode(ISD::OR, dl, IntValTy, And0, And1);
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return DAG.getNode(ISD::BITCAST, dl, ValTy, Result);
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static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
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EVT TyX = Op.getOperand(0).getValueType();
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EVT TyY = Op.getOperand(1).getValueType();
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SDValue Const1 = DAG.getConstant(1, MVT::i32);
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SDValue Const31 = DAG.getConstant(31, MVT::i32);
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DebugLoc DL = Op.getDebugLoc();
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SDValue Res;
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// If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
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// to i32.
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SDValue X = (TyX == MVT::f32) ?
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DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
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DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
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Const1);
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SDValue Y = (TyY == MVT::f32) ?
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DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
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DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
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Const1);
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if (HasR2) {
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// ext E, Y, 31, 1 ; extract bit31 of Y
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// ins X, E, 31, 1 ; insert extracted bit at bit31 of X
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SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
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Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
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} else {
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// sll SllX, X, 1
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// srl SrlX, SllX, 1
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// srl SrlY, Y, 31
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// sll SllY, SrlX, 31
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// or Or, SrlX, SllY
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SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
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SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
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SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
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SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
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Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
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}
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if (TyX == MVT::f32)
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return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
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SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
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Op.getOperand(0), DAG.getConstant(0, MVT::i32));
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return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
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}
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// Called if the size of integer registers is not large enough to hold the whole
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// floating point number (e.g. f64 & 32-bit integer register).
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static SDValue
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LowerFCOPYSIGNSmallIntReg(SDValue Op, SelectionDAG &DAG, bool isLittle) {
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// FIXME:
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// Use ext/ins instructions if target architecture is Mips32r2.
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// Eliminate redundant mfc1 and mtc1 instructions.
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unsigned LoIdx = 0, HiIdx = 1;
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static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
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unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
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unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
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EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
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SDValue Const1 = DAG.getConstant(1, MVT::i32);
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DebugLoc DL = Op.getDebugLoc();
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if (!isLittle)
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std::swap(LoIdx, HiIdx);
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// Bitcast to integer nodes.
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SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
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SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
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DebugLoc dl = Op.getDebugLoc();
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SDValue Word0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
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Op.getOperand(0),
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DAG.getConstant(LoIdx, MVT::i32));
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SDValue Hi0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
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Op.getOperand(0), DAG.getConstant(HiIdx, MVT::i32));
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SDValue Hi1 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
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Op.getOperand(1), DAG.getConstant(HiIdx, MVT::i32));
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SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi0,
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DAG.getConstant(0x7fffffff, MVT::i32));
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SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi1,
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DAG.getConstant(0x80000000, MVT::i32));
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SDValue Word1 = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1);
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if (HasR2) {
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// ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
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// ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
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SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
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DAG.getConstant(WidthY - 1, MVT::i32), Const1);
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if (!isLittle)
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std::swap(Word0, Word1);
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if (WidthX > WidthY)
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E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
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else if (WidthY > WidthX)
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E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
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return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1);
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SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
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DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
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return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
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}
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// (d)sll SllX, X, 1
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// (d)srl SrlX, SllX, 1
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// (d)srl SrlY, Y, width(Y)-1
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// (d)sll SllY, SrlX, width(Y)-1
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// or Or, SrlX, SllY
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SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
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SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
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SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
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DAG.getConstant(WidthY - 1, MVT::i32));
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if (WidthX > WidthY)
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SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
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else if (WidthY > WidthX)
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SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
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SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
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DAG.getConstant(WidthX - 1, MVT::i32));
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SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
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return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
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}
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SDValue
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MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
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EVT Ty = Op.getValueType();
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if (Subtarget->hasMips64())
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return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
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assert(Ty == MVT::f32 || Ty == MVT::f64);
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if (Ty == MVT::f32 || HasMips64)
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return LowerFCOPYSIGNLargeIntReg(Op, DAG);
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return LowerFCOPYSIGNSmallIntReg(Op, DAG, Subtarget->isLittle());
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return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
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}
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SDValue MipsTargetLowering::
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50
test/CodeGen/Mips/fcopysign-f32-f64.ll
Normal file
50
test/CodeGen/Mips/fcopysign-f32-f64.ll
Normal file
@ -0,0 +1,50 @@
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=64
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; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2
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declare double @copysign(double, double) nounwind readnone
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declare float @copysignf(float, float) nounwind readnone
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define float @func2(float %d, double %f) nounwind readnone {
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entry:
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; 64: func2
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; 64: lui $[[T0:[0-9]+]], 32767
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; 64: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
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; 64: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
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; 64: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 63
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; 64: sll $[[SLL:[0-9]+]], ${{[0-9]+}}, 31
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; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[SLL]]
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; 64: mtc1 $[[OR]], $f0
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; 64R2: dext ${{[0-9]+}}, ${{[0-9]+}}, 63, 1
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; 64R2: ins $[[INS:[0-9]+]], ${{[0-9]+}}, 31, 1
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; 64R2: mtc1 $[[INS]], $f0
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%add = fadd float %d, 1.000000e+00
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%conv = fptrunc double %f to float
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%call = tail call float @copysignf(float %add, float %conv) nounwind readnone
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ret float %call
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}
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define double @func3(double %d, float %f) nounwind readnone {
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entry:
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; 64: daddiu $[[T0:[0-9]+]], $zero, 1
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; 64: dsll $[[T1:[0-9]+]], $[[T0]], 63
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; 64: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1
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; 64: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
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; 64: srl ${{[0-9]+}}, ${{[0-9]+}}, 31
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; 64: dsll $[[DSLL:[0-9]+]], ${{[0-9]+}}, 63
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; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
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; 64: dmtc1 $[[OR]], $f0
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; 64R2: ext ${{[0-9]+}}, ${{[0-9]+}}, 31, 1
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; 64R2: dins $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1
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; 64R2: dmtc1 $[[INS]], $f0
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%add = fadd double %d, 1.000000e+00
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%conv = fpext float %f to double
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%call = tail call double @copysign(double %add, double %conv) nounwind readnone
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ret double %call
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}
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@ -1,40 +1,35 @@
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; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=MIPS32-EL
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; RUN: llc < %s -march=mips | FileCheck %s -check-prefix=MIPS32-EB
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=MIPS64
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; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=32
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=64
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; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2
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define double @func0(double %d0, double %d1) nounwind readnone {
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entry:
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; MIPS32-EL: func0:
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; MIPS32-EL: mfc1 $[[HI0:[0-9]+]], $f15
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; MIPS32-EL: lui $[[MSK1:[0-9]+]], 32768
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; MIPS32-EL: and $[[AND1:[0-9]+]], $[[HI0]], $[[MSK1]]
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; MIPS32-EL: lui $[[T0:[0-9]+]], 32767
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; MIPS32-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
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; MIPS32-EL: mfc1 $[[HI1:[0-9]+]], $f13
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; MIPS32-EL: and $[[AND0:[0-9]+]], $[[HI1]], $[[MSK0]]
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; MIPS32-EL: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
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; MIPS32-EL: mfc1 $[[LO0:[0-9]+]], $f12
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; MIPS32-EL: mtc1 $[[LO0]], $f0
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; MIPS32-EL: mtc1 $[[OR]], $f1
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;
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; MIPS32-EB: mfc1 $[[HI1:[0-9]+]], $f14
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; MIPS32-EB: lui $[[MSK1:[0-9]+]], 32768
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; MIPS32-EB: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
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; MIPS32-EB: lui $[[T0:[0-9]+]], 32767
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; MIPS32-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
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; MIPS32-EB: mfc1 $[[HI0:[0-9]+]], $f12
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; MIPS32-EB: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
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; MIPS32-EB: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
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; MIPS32-EB: mfc1 $[[LO0:[0-9]+]], $f13
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; MIPS32-EB: mtc1 $[[OR]], $f0
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; MIPS32-EB: mtc1 $[[LO0]], $f1
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; 32: lui $[[MSK1:[0-9]+]], 32768
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; 32: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]]
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; 32: lui $[[T0:[0-9]+]], 32767
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; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
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; 32: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
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; 32: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
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; 32: mtc1 $[[OR]], $f1
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; 32R2: ext $[[EXT:[0-9]+]], ${{[0-9]+}}, 31, 1
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; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1
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; 32R2: mtc1 $[[INS]], $f1
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; 64: daddiu $[[T0:[0-9]+]], $zero, 1
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; 64: dsll $[[MSK1:[0-9]+]], $[[T0]], 63
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; 64: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]]
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; 64: daddiu $[[MSK0:[0-9]+]], $[[MSK1]], -1
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; 64: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
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; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
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; 64: dmtc1 $[[OR]], $f0
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; 64R2: dext $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1
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; 64R2: dins $[[INS:[0-9]+]], $[[EXT]], 63, 1
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; 64R2: dmtc1 $[[INS]], $f0
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; MIPS64: dmfc1 $[[R0:[0-9]+]], $f13
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; MIPS64: and $[[R1:[0-9]+]], $[[R0]], ${{[0-9]+}}
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; MIPS64: dmfc1 $[[R2:[0-9]+]], $f12
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; MIPS64: and $[[R3:[0-9]+]], $[[R2]], ${{[0-9]+}}
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; MIPS64: or $[[R4:[0-9]+]], $[[R3]], $[[R1]]
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; MIPS64: dmtc1 $[[R4]], $f0
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%call = tail call double @copysign(double %d0, double %d1) nounwind readnone
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ret double %call
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}
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@ -43,18 +38,22 @@ declare double @copysign(double, double) nounwind readnone
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define float @func1(float %f0, float %f1) nounwind readnone {
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entry:
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; MIPS32-EL: func1:
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; MIPS32-EL: mfc1 $[[ARG1:[0-9]+]], $f14
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; MIPS32-EL: lui $[[MSK1:[0-9]+]], 32768
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; MIPS32-EL: and $[[T3:[0-9]+]], $[[ARG1]], $[[MSK1]]
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; MIPS32-EL: lui $[[T0:[0-9]+]], 32767
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; MIPS32-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
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; MIPS32-EL: mfc1 $[[ARG0:[0-9]+]], $f12
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; MIPS32-EL: and $[[T2:[0-9]+]], $[[ARG0]], $[[MSK0]]
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; MIPS32-EL: or $[[T4:[0-9]+]], $[[T2]], $[[T3]]
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; MIPS32-EL: mtc1 $[[T4]], $f0
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; 32: lui $[[MSK1:[0-9]+]], 32768
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; 32: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]]
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; 32: lui $[[T0:[0-9]+]], 32767
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; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
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; 32: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
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; 32: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
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; 32: mtc1 $[[OR]], $f0
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; 32R2: ext $[[EXT:[0-9]+]], ${{[0-9]+}}, 31, 1
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; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1
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; 32R2: mtc1 $[[INS]], $f0
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%call = tail call float @copysignf(float %f0, float %f1) nounwind readnone
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ret float %call
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}
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declare float @copysignf(float, float) nounwind readnone
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