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Fix assert(0) conversion, as suggested by Chris.
llvm-svn: 75423
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29416147f7
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67153904ec
@ -1132,10 +1132,10 @@ void IfConverter::PredicateBlock(BBInfo &BBI,
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if (TII->isPredicated(I))
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continue;
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if (!TII->PredicateInstruction(I, Cond)) {
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std::string msg;
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raw_string_ostream Msg(msg);
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Msg << "Unable to predicate " << *I << "!";
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llvm_report_error(Msg.str());
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#ifndef NDEBUG
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cerr << "Unable to predicate " << *I << "!\n";
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#endif
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llvm_unreachable();
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}
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}
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@ -1168,10 +1168,10 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
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if (!isPredicated)
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if (!TII->PredicateInstruction(MI, Cond)) {
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std::string msg;
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raw_string_ostream Msg(msg);
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Msg << "Unable to predicate " << *MI << "!";
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llvm_report_error(Msg.str());
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#ifndef NDEBUG
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cerr << "Unable to predicate " << *I << "!\n";
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#endif
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llvm_unreachable();
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}
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}
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@ -1035,10 +1035,7 @@ bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
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CurrLI->FindLiveRangeContaining(LIs->getUseIndex(BarrierIdx));
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VNInfo *ValNo = LR->valno;
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if (ValNo->isUnused()) {
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// Defined by a dead def? How can this be?
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LLVM_UNREACHABLE("Val# is defined by a dead def?");
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}
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assert(!ValNo->isUnused() && "Val# is defined by a dead def?");
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MachineInstr *DefMI = ValNo->isDefAccurate()
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? LIs->getInstructionFromIndex(ValNo->def) : NULL;
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@ -459,9 +459,8 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
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Reg = Candidates.find_next(Reg);
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}
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if (ScavengedReg != 0) {
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LLVM_UNREACHABLE("Scavenger slot is live, unable to scavenge another register!");
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}
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assert(ScavengedReg == 0 &&
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"Scavenger slot is live, unable to scavenge another register!");
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// Spill the scavenged register before I.
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TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
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@ -152,9 +152,12 @@ namespace llvm {
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// basic blocks, and the scheduler passes ownership of it to this method.
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MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const {
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llvm_report_error("If a target marks an instruction with "
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"'usesCustomDAGSchedInserter', it must implement "
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"TargetLowering::EmitInstrWithCustomInserter!");
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#ifndef NDEBUG
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cerr << "If a target marks an instruction with "
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"'usesCustomDAGSchedInserter', it must implement "
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"TargetLowering::EmitInstrWithCustomInserter!";
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#endif
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llvm_unreachable();
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return 0;
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}
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@ -831,8 +834,8 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
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cerr << "FastISel miss: ";
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BI->dump();
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}
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if (EnableFastISelAbort)
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LLVM_UNREACHABLE("FastISel didn't handle a PHI in a successor");
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assert(!EnableFastISelAbort &&
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"FastISel didn't handle a PHI in a successor");
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break;
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}
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