mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-12-21 02:59:15 +00:00
Don't use DebugLoc::getUnknownLoc(). Default to something hopefully sensible.
llvm-svn: 63473
This commit is contained in:
Bill Wendling
parent
235913be77
commit
679d743429
@ -1947,7 +1947,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
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SDValue NewPtr = LN0->getBasePtr();
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if (TLI.isBigEndian()) {
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NewPtr = DAG.getNode(ISD::ADD, DebugLoc::getUnknownLoc(), PtrType,
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NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
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NewPtr, DAG.getConstant(PtrOff, PtrType));
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Alignment = MinAlign(Alignment, PtrOff);
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}
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@ -2636,9 +2636,11 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
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uint64_t TruncC = TruncVT.getIntegerVTBitMask() &
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N101C->getZExtValue();
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return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
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DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(),
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DAG.getNode(ISD::AND, N->getDebugLoc(),
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TruncVT,
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DAG.getNode(ISD::TRUNCATE, TruncVT, N100),
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DAG.getNode(ISD::TRUNCATE,
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N->getDebugLoc(),
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TruncVT, N100),
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DAG.getConstant(TruncC, TruncVT)));
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}
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}
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@ -2759,9 +2761,11 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
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uint64_t TruncC = TruncVT.getIntegerVTBitMask() &
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N101C->getZExtValue();
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return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
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DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(),
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DAG.getNode(ISD::AND, N->getDebugLoc(),
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TruncVT,
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DAG.getNode(ISD::TRUNCATE, TruncVT, N100),
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DAG.getNode(ISD::TRUNCATE,
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N->getDebugLoc(),
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TruncVT, N100),
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DAG.getConstant(TruncC, TruncVT)));
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}
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}
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@ -3092,12 +3096,12 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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if (SOp == Trunc)
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Ops.push_back(ExtLoad);
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else
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Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, DebugLoc::getUnknownLoc(),
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Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
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VT, SOp));
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}
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Ops.push_back(SetCC->getOperand(2));
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CombineTo(SetCC, DAG.getNode(ISD::SETCC, DebugLoc::getUnknownLoc(),
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CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
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SetCC->getValueType(0),
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&Ops[0], Ops.size()));
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}
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@ -3174,9 +3178,9 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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(!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
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SDValue Op = N0.getOperand(0);
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if (Op.getValueType().bitsLT(VT)) {
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Op = DAG.getNode(ISD::ANY_EXTEND, DebugLoc::getUnknownLoc(), VT, Op);
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Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
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} else if (Op.getValueType().bitsGT(VT)) {
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Op = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, Op);
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Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
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}
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return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType());
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}
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@ -3187,9 +3191,9 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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N0.getOperand(1).getOpcode() == ISD::Constant) {
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SDValue X = N0.getOperand(0).getOperand(0);
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if (X.getValueType().bitsLT(VT)) {
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X = DAG.getNode(ISD::ANY_EXTEND, DebugLoc::getUnknownLoc(), VT, X);
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X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
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} else if (X.getValueType().bitsGT(VT)) {
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X = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, X);
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X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
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}
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APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
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Mask.zext(VT.getSizeInBits());
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@ -3228,11 +3232,12 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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if (SOp == Trunc)
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Ops.push_back(ExtLoad);
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else
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Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp));
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Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND,
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N->getDebugLoc(), VT, SOp));
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}
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Ops.push_back(SetCC->getOperand(2));
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CombineTo(SetCC, DAG.getNode(ISD::SETCC, DebugLoc::getUnknownLoc(),
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CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
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SetCC->getValueType(0),
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&Ops[0], Ops.size()));
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}
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@ -3317,9 +3322,9 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
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N0.getOperand(1).getOpcode() == ISD::Constant) {
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SDValue X = N0.getOperand(0).getOperand(0);
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if (X.getValueType().bitsLT(VT)) {
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X = DAG.getNode(ISD::ANY_EXTEND, DebugLoc::getUnknownLoc(), VT, X);
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X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
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} else if (X.getValueType().bitsGT(VT)) {
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X = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, X);
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X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
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}
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APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
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Mask.zext(VT.getSizeInBits());
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@ -3476,7 +3481,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
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uint64_t PtrOff = ShAmt / 8;
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unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
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SDValue NewPtr = DAG.getNode(ISD::ADD, DebugLoc::getUnknownLoc(),
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SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
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PtrType, LN0->getBasePtr(),
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DAG.getConstant(PtrOff, PtrType));
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AddToWorkList(NewPtr.getNode());
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@ -3773,34 +3778,34 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
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unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
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MVT IntXVT = MVT::getIntegerVT(OrigXWidth);
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if (TLI.isTypeLegal(IntXVT) || !LegalTypes) {
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SDValue X = DAG.getNode(ISD::BIT_CONVERT, DebugLoc::getUnknownLoc(),
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SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
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IntXVT, N0.getOperand(1));
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AddToWorkList(X.getNode());
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// If X has a different width than the result/lhs, sext it or truncate it.
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unsigned VTWidth = VT.getSizeInBits();
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if (OrigXWidth < VTWidth) {
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X = DAG.getNode(ISD::SIGN_EXTEND, DebugLoc::getUnknownLoc(), VT, X);
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X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
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AddToWorkList(X.getNode());
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} else if (OrigXWidth > VTWidth) {
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// To get the sign bit in the right place, we have to shift it right
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// before truncating.
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X = DAG.getNode(ISD::SRL, DebugLoc::getUnknownLoc(),
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X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
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X.getValueType(), X,
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DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
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AddToWorkList(X.getNode());
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X = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, X);
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X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
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AddToWorkList(X.getNode());
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}
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APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
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X = DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(), VT,
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X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
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X, DAG.getConstant(SignBit, VT));
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AddToWorkList(X.getNode());
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SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, DebugLoc::getUnknownLoc(),
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SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
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VT, N0.getOperand(0));
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Cst = DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(), VT,
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Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
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Cst, DAG.getConstant(~SignBit, VT));
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AddToWorkList(Cst.getNode());
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@ -3897,8 +3902,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) {
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}
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if (EltIsUndef)
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Ops.push_back(DAG.getNode(ISD::UNDEF, DebugLoc::getUnknownLoc(),
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DstEltVT));
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Ops.push_back(DAG.getNode(ISD::UNDEF, BV->getDebugLoc(), DstEltVT));
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else
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Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
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}
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@ -3918,8 +3922,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) {
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for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
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if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
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for (unsigned j = 0; j != NumOutputsPerInput; ++j)
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Ops.push_back(DAG.getNode(ISD::UNDEF, DebugLoc::getUnknownLoc(),
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DstEltVT));
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Ops.push_back(DAG.getNode(ISD::UNDEF, BV->getDebugLoc(), DstEltVT));
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continue;
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}
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@ -4136,8 +4139,7 @@ SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
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} else {
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if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
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return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
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DAG.getNode(ISD::FABS, DebugLoc::getUnknownLoc(),
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VT, N0));
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DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
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}
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}
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@ -4349,7 +4351,7 @@ SDValue DAGCombiner::visitFNEG(SDNode *N) {
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SDValue Int = N0.getOperand(0);
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MVT IntVT = Int.getValueType();
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if (IntVT.isInteger() && !IntVT.isVector()) {
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Int = DAG.getNode(ISD::XOR, DebugLoc::getUnknownLoc(), IntVT, Int,
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Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
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DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT));
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AddToWorkList(Int.getNode());
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return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
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@ -4384,7 +4386,7 @@ SDValue DAGCombiner::visitFABS(SDNode *N) {
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SDValue Int = N0.getOperand(0);
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MVT IntVT = Int.getValueType();
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if (IntVT.isInteger() && !IntVT.isVector()) {
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Int = DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(), IntVT, Int,
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Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
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DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT));
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AddToWorkList(Int.getNode());
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return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
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@ -4807,8 +4809,8 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) {
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WorkListRemover DeadNodes(*this);
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DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
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DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
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DAG.getNode(ISD::UNDEF, DebugLoc::getUnknownLoc(),
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N->getValueType(1)),
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DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
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N->getValueType(1)),
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&DeadNodes);
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DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
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removeFromWorkList(N);
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@ -5230,7 +5232,7 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
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for (unsigned i = 0; i != NumInScalars; ++i) {
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if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
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BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF,
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DebugLoc::getUnknownLoc(),
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N->getDebugLoc(),
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TLI.getPointerTy()));
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continue;
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}
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@ -5460,13 +5462,13 @@ SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
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MVT VT = MVT::getVectorVT(EVT, NumElts);
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MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts);
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std::vector<SDValue> Ops;
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LHS = DAG.getNode(ISD::BIT_CONVERT, DebugLoc::getUnknownLoc(), VT, LHS);
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LHS = DAG.getNode(ISD::BIT_CONVERT, LHS.getDebugLoc(), VT, LHS);
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Ops.push_back(LHS);
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AddToWorkList(LHS.getNode());
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std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT));
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Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(),
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Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
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VT, &ZeroOps[0], ZeroOps.size()));
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Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(),
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Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
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MaskVT, &IdxOps[0], IdxOps.size()));
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SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(),
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VT, &Ops[0], Ops.size());
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@ -5525,7 +5527,7 @@ SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
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break;
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}
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Ops.push_back(DAG.getNode(N->getOpcode(), DebugLoc::getUnknownLoc(),
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Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(),
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EltType, LHSOp, RHSOp));
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AddToWorkList(Ops.back().getNode());
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assert((Ops.back().getOpcode() == ISD::UNDEF ||
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@ -5721,28 +5723,26 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
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unsigned ShCtV = N2C->getAPIntValue().logBase2();
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ShCtV = XType.getSizeInBits()-ShCtV-1;
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SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
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SDValue Shift = DAG.getNode(ISD::SRL, DebugLoc::getUnknownLoc(),
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SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
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XType, N0, ShCt);
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AddToWorkList(Shift.getNode());
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if (XType.bitsGT(AType)) {
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Shift = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(),
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AType, Shift);
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Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
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AddToWorkList(Shift.getNode());
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}
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return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
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}
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SDValue Shift = DAG.getNode(ISD::SRA, DebugLoc::getUnknownLoc(),
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SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
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XType, N0,
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DAG.getConstant(XType.getSizeInBits()-1,
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TLI.getShiftAmountTy()));
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AddToWorkList(Shift.getNode());
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if (XType.bitsGT(AType)) {
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Shift = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(),
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AType, Shift);
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Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
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AddToWorkList(Shift.getNode());
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}
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@ -5765,18 +5765,16 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
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SDValue Temp, SCC;
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// cast from setcc result type to select result type
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if (LegalTypes) {
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SCC = DAG.getSetCC(DebugLoc::getUnknownLoc(),
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TLI.getSetCCResultType(N0.getValueType()),
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SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
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N0, N1, CC);
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if (N2.getValueType().bitsLT(SCC.getValueType()))
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Temp = DAG.getZeroExtendInReg(SCC, DebugLoc::getUnknownLoc(),
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N2.getValueType());
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Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
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else
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Temp = DAG.getNode(ISD::ZERO_EXTEND, DebugLoc::getUnknownLoc(),
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Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
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N2.getValueType(), SCC);
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} else {
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SCC = DAG.getSetCC(DebugLoc::getUnknownLoc(), MVT::i1, N0, N1, CC);
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Temp = DAG.getNode(ISD::ZERO_EXTEND, DebugLoc::getUnknownLoc(),
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SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
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Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
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N2.getValueType(), SCC);
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}
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@ -5809,8 +5807,7 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
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if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
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(!LegalOperations ||
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TLI.isOperationLegal(ISD::CTLZ, XType))) {
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SDValue Ctlz = DAG.getNode(ISD::CTLZ, DebugLoc::getUnknownLoc(),
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XType, N0);
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SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
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return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
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DAG.getConstant(Log2_32(XType.getSizeInBits()),
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TLI.getShiftAmountTy()));
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@ -5827,7 +5824,7 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
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}
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// fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
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if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
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SDValue Sign = DAG.getNode(ISD::SRL, DebugLoc::getUnknownLoc(), XType, N0,
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SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
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DAG.getConstant(XType.getSizeInBits()-1,
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TLI.getShiftAmountTy()));
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return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
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@ -5840,10 +5837,10 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
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N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
|
||||
N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
|
||||
MVT XType = N0.getValueType();
|
||||
SDValue Shift = DAG.getNode(ISD::SRA, DebugLoc::getUnknownLoc(), XType, N0,
|
||||
SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0,
|
||||
DAG.getConstant(XType.getSizeInBits()-1,
|
||||
TLI.getShiftAmountTy()));
|
||||
SDValue Add = DAG.getNode(ISD::ADD, DebugLoc::getUnknownLoc(), XType,
|
||||
SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType,
|
||||
N0, Shift);
|
||||
AddToWorkList(Shift.getNode());
|
||||
AddToWorkList(Add.getNode());
|
||||
@ -5856,11 +5853,11 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
|
||||
if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
|
||||
MVT XType = N0.getValueType();
|
||||
if (SubC->isNullValue() && XType.isInteger()) {
|
||||
SDValue Shift = DAG.getNode(ISD::SRA, DebugLoc::getUnknownLoc(), XType,
|
||||
SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
|
||||
N0,
|
||||
DAG.getConstant(XType.getSizeInBits()-1,
|
||||
TLI.getShiftAmountTy()));
|
||||
SDValue Add = DAG.getNode(ISD::ADD, DebugLoc::getUnknownLoc(),
|
||||
SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
|
||||
XType, N0, Shift);
|
||||
AddToWorkList(Shift.getNode());
|
||||
AddToWorkList(Add.getNode());
|
||||
|
||||
Loading…
Reference in New Issue
Block a user