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Some minor updates to atomic acquire/release docs in LangRef.
llvm-svn: 138472
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@ -1634,14 +1634,15 @@ address is written <code>monotonic</code>ally by one thread, and other threads
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eventually see the write. This corresponds to the C++0x/C1x
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eventually see the write. This corresponds to the C++0x/C1x
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<code>memory_order_relaxed</code>.</dd>
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<code>memory_order_relaxed</code>.</dd>
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<dt><code>acquire</code></dt>
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<dt><code>acquire</code></dt>
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<dd>In addition to the guarantees of <code>monotonic</code>, if this operation
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reads a value written by a <code>release</code> atomic operation, it
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<i>synchronizes-with</i> that operation. This corresponds to the C++0x/C1x
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<code>memory_order_acquire</code>.</dd>
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<dt><code>release</code></dt>
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<dd>In addition to the guarantees of <code>monotonic</code>,
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<dd>In addition to the guarantees of <code>monotonic</code>,
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a <i>synchronizes-with</i> edge may be formed with an <code>acquire</code>
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a <i>synchronizes-with</i> edge may be formed with a <code>release</code>
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operation. This is intended to model C++'s <code>memory_order_release</code>.</dd>
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operation. This is intended to model C++'s <code>memory_order_acquire</code>.</dd>
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<dt><code>release</code></dt>
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<dd>In addition to the guarantees of <code>monotonic</code>, if this operation
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writes a value which is subsequently read by an <code>acquire</code> operation,
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it <i>synchronizes-with</i> that operation. (This isn't a complete
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description; see the C++0x definition of a release sequence.) This corresponds
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to the C++0x/C1x <code>memory_order_release</code>.</dd>
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<dt><code>acq_rel</code> (acquire+release)</dt><dd>Acts as both an
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<dt><code>acq_rel</code> (acquire+release)</dt><dd>Acts as both an
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<code>acquire</code> and <code>release</code> operation on its address.
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<code>acquire</code> and <code>release</code> operation on its address.
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This corresponds to the C++0x/C1x <code>memory_order_acq_rel</code>.</dd>
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This corresponds to the C++0x/C1x <code>memory_order_acq_rel</code>.</dd>
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