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Stop using the old pre-UAL syntax for LDM/STM instruction suffixes.

Browse Source 
This does not move entirely to UAL syntax, since the default "increment after"
suffix is empty but we still use "IA" for that.

llvm-svn: 98635
This commit is contained in:
Bob Wilson 2010-03-16 16:19:07 +00:00
parent b938a147c9
commit 67c88e4977
10 changed files with 10 additions and 38 deletions
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10
lib/Target/ARM/ARMAddressingModes.h
View File

@ -78,16 +78,6 @@ namespace ARM_AM {
}
}
static inline const char *getAMSubModeAltStr(AMSubMode Mode, bool isLD) {
switch (Mode) {
default: assert(0 && "Unknown addressing sub-mode!");
case ARM_AM::ia: return isLD ? "fd" : "ea";
case ARM_AM::ib: return isLD ? "ed" : "fa";
case ARM_AM::da: return isLD ? "fa" : "ed";
case ARM_AM::db: return isLD ? "ea" : "fd";
}
}
/// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
///
static inline unsigned rotr32(unsigned Val, unsigned Amt) {

12
lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
View File

@ -518,17 +518,7 @@ void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
const MachineOperand &MO2 = MI->getOperand(Op+1);
ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
if (Modifier && strcmp(Modifier, "submode") == 0) {
if (MO1.getReg() == ARM::SP) {
// FIXME
bool isLDM = (MI->getOpcode() == ARM::LDM ||
MI->getOpcode() == ARM::LDM_UPD ||
MI->getOpcode() == ARM::LDM_RET ||
MI->getOpcode() == ARM::t2LDM ||
MI->getOpcode() == ARM::t2LDM_UPD ||
MI->getOpcode() == ARM::t2LDM_RET);
O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
} else
O << ARM_AM::getAMSubModeStr(Mode);
O << ARM_AM::getAMSubModeStr(Mode);
} else if (Modifier && strcmp(Modifier, "wide") == 0) {
ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
if (Mode == ARM_AM::ia)

10
lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
View File

@ -226,15 +226,7 @@ void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum,
const MCOperand &MO2 = MI->getOperand(OpNum+1);
ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
if (Modifier && strcmp(Modifier, "submode") == 0) {
if (MO1.getReg() == ARM::SP) {
// FIXME
bool isLDM = (MI->getOpcode() == ARM::LDM ||
MI->getOpcode() == ARM::LDM_RET ||
MI->getOpcode() == ARM::t2LDM ||
MI->getOpcode() == ARM::t2LDM_RET);
O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
} else
O << ARM_AM::getAMSubModeStr(Mode);
O << ARM_AM::getAMSubModeStr(Mode);
} else if (Modifier && strcmp(Modifier, "wide") == 0) {
ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
if (Mode == ARM_AM::ia)

2
test/CodeGen/ARM/ifcvt5.ll
View File

@ -11,7 +11,7 @@ entry:
define void @t1(i32 %a, i32 %b) {
; CHECK: t1:
; CHECK: ldmfdlt sp!, {r7, pc}
; CHECK: ldmialt sp!, {r7, pc}
entry:
%tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1]
br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock

2
test/CodeGen/ARM/ifcvt6.ll
View File

@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
; RUN: grep cmpne | count 1
; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
; RUN: grep ldmfdhi | count 1
; RUN: grep ldmiahi | count 1
define void @foo(i32 %X, i32 %Y) {
entry:

2
test/CodeGen/ARM/ifcvt7.ll
View File

@ -3,7 +3,7 @@
; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
; RUN: grep moveq | count 1
; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
; RUN: grep ldmfdeq | count 1
; RUN: grep ldmiaeq | count 1
; FIXME: Need post-ifcvt branch folding to get rid of the extra br at end of BB1.
%struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* }

2
test/CodeGen/ARM/ifcvt8.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
; RUN: grep ldmfdne | count 1
; RUN: grep ldmiane | count 1
%struct.SString = type { i8*, i32, i32 }

2
test/CodeGen/ARM/ldm.ll
View File

@ -24,7 +24,7 @@ define i32 @t2() {
define i32 @t3() {
; CHECK: t3:
; CHECK: ldmib
; CHECK: ldmfd sp!
; CHECK: ldmia sp!
%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1]
%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
%tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]

4
test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll
View File

@ -12,10 +12,10 @@
define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) {
; CHECK: _ZNKSs7compareERKSs:
; CHECK: it ne
; CHECK-NEXT: ldmfdne.w
; CHECK-NEXT: ldmiane.w
; CHECK-NEXT: itt eq
; CHECK-NEXT: subeq.w
; CHECK-NEXT: ldmfdeq.w
; CHECK-NEXT: ldmiaeq.w
entry:
%0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i32> [#uses=3]
%1 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i32> [#uses=3]

2
test/CodeGen/Thumb2/large-stack.ll
View File

@ -27,7 +27,7 @@ define i32 @test3() {
; DARWIN: sub.w sp, sp, #805306368
; DARWIN: sub sp, #20
; LINUX: test3:
; LINUX: stmfd sp!, {r4, r7, r11, lr}
; LINUX: stmdb sp!, {r4, r7, r11, lr}
; LINUX: sub.w sp, sp, #805306368
; LINUX: sub sp, #16
%retval = alloca i32, align 4