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Handle perfect shuffle case that generates a vrev for vectors of floats.
Add test case. llvm-svn: 131582
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@ -4184,7 +4184,8 @@ static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
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default: llvm_unreachable("Unknown shuffle opcode!");
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case OP_VREV:
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// VREV divides the vector in half and swaps within the half.
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if (VT.getVectorElementType() == MVT::i32)
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if (VT.getVectorElementType() == MVT::i32 ||
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VT.getVectorElementType() == MVT::f32)
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return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
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// vrev <4 x i16> -> VREV32
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if (VT.getVectorElementType() == MVT::i16)
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@ -163,3 +163,18 @@ entry:
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store <2 x i16> %tmp11, <2 x i16>* %dst, align 4
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ret void
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}
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; Test vrev of float4
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define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest) nounwind noinline ssp {
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; CHECK: float_vrev64
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; CHECK: vext.32
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; CHECK: vrev64.32
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entry:
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%0 = bitcast float* %source to <4 x float>*
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%tmp2 = load <4 x float>* %0, align 4
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%tmp5 = shufflevector <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x float> %tmp2, <4 x i32> <i32 0, i32 7, i32 0, i32 0>
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%arrayidx8 = getelementptr inbounds <4 x float>* %dest, i32 11
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store <4 x float> %tmp5, <4 x float>* %arrayidx8, align 4
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ret void
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}
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