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Rename reloads/spills to loads/stores.

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llvm-svn: 11619
This commit is contained in:
Alkis Evlogimenos 2004-02-19 06:19:09 +00:00
parent ef9c4f4339
commit 68f40cbfd3
3 changed files with 14 additions and 14 deletions
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10
lib/CodeGen/RegAllocLinearScan.cpp
View File

@ -31,8 +31,8 @@
using namespace llvm;
namespace {
Statistic<> numSpilled ("ra-linearscan", "Number of registers spilled");
Statistic<> numReloaded("ra-linearscan", "Number of registers reloaded");
Statistic<> numStores("ra-linearscan", "Number of stores added");
Statistic<> numLoads ("ra-linearscan", "Number of loads added");
class PhysRegTracker {
private:
@ -650,7 +650,7 @@ void RA::addSpillCode(IntervalPtrs::value_type li, int slot)
DEBUG(std::cerr << "add store for reg" << li->reg << " to "
"stack slot " << slot << " after: ";
mi->print(std::cerr, *tm_));
++numSpilled;
++numStores;
mri_->storeRegToStackSlot(*mi->getParent(),
next(mi), li->reg, slot, rc);
}
@ -666,7 +666,7 @@ void RA::addSpillCode(IntervalPtrs::value_type li, int slot)
DEBUG(std::cerr << "add load for reg" << li->reg
<< " from stack slot " << slot << " before: ";
mi->print(std::cerr, *tm_));
++numReloaded;
++numLoads;
mri_->loadRegFromStackSlot(*mi->getParent(),
mi, li->reg, slot, rc);
}
@ -687,7 +687,7 @@ void RA::addSpillCode(IntervalPtrs::value_type li, int slot)
DEBUG(std::cerr << "add store for reg" << li->reg << " to "
"stack slot " << slot << " after: ";
mi->print(std::cerr, *tm_));
++numSpilled;
++numStores;
mri_->storeRegToStackSlot(*mi->getParent(),
next(mi), li->reg, slot, rc);
}

10
lib/CodeGen/RegAllocLocal.cpp
View File

@ -28,9 +28,9 @@
using namespace llvm;
namespace {
Statistic<> NumSpilled ("ra-local", "Number of registers spilled");
Statistic<> NumReloaded("ra-local", "Number of registers reloaded");
Statistic<> NumFused ("ra-local", "Number of reloads fused into instructions");
Statistic<> NumStores("ra-local", "Number of stores added");
Statistic<> NumLoads ("ra-local", "Number of loads added");
Statistic<> NumFused ("ra-local", "Number of reloads fused into instructions");
class RA : public MachineFunctionPass {
const TargetMachine *TM;
MachineFunction *MF;
@ -275,7 +275,7 @@ void RA::spillVirtReg(MachineBasicBlock &MBB, MachineInstr *I,
int FrameIndex = getStackSpaceFor(VirtReg, RC);
DEBUG(std::cerr << " to stack slot #" << FrameIndex);
RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
++NumSpilled; // Update statistics
++NumStores; // Update statistics
}
getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available
@ -512,7 +512,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
// Add move instruction(s)
RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
++NumReloaded; // Update statistics
++NumLoads; // Update statistics
MI->SetMachineOperandReg(OpNum, PhysReg); // Assign the input register
return MI;

8
lib/CodeGen/RegAllocSimple.cpp
View File

@ -28,8 +28,8 @@
using namespace llvm;
namespace {
Statistic<> NumSpilled ("ra-simple", "Number of registers spilled");
Statistic<> NumReloaded("ra-simple", "Number of registers reloaded");
Statistic<> NumStores("ra-simple", "Number of stores added");
Statistic<> NumLoads ("ra-simple", "Number of loads added");
class RegAllocSimple : public MachineFunctionPass {
MachineFunction *MF;
@ -130,7 +130,7 @@ unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
unsigned PhysReg = getFreeReg(VirtReg);
// Add move instruction(s)
++NumReloaded;
++NumLoads;
RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
return PhysReg;
}
@ -142,7 +142,7 @@ void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
int FrameIdx = getStackSpaceFor(VirtReg, RC);
// Add move instruction(s)
++NumSpilled;
++NumStores;
RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC);
}