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[PowerPC] set optimization level in SelectionDAGISel
PowerPC backend does not pass the current optimization level to SelectionDAGISel and so SelectionDAGISel works with the default optimization level regardless of the current optimization level. This patch makes the PowerPC backend set the optimization level correctly. Differential Revision: https://reviews.llvm.org/D34615 llvm-svn: 306367
This commit is contained in:
Hiroshi Inoue
parent
8db5a8c13f
commit
69391ac868
@ -15,6 +15,7 @@
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#ifndef LLVM_LIB_TARGET_POWERPC_PPC_H
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#define LLVM_LIB_TARGET_POWERPC_PPC_H
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#include "llvm/Support/CodeGen.h"
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#include "MCTargetDesc/PPCMCTargetDesc.h"
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// GCC #defines PPC on Linux but we use it as our namespace name
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@ -41,7 +42,7 @@ namespace llvm {
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FunctionPass *createPPCMIPeepholePass();
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FunctionPass *createPPCBranchSelectionPass();
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FunctionPass *createPPCQPXLoadSplatPass();
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FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
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FunctionPass *createPPCISelDag(PPCTargetMachine &TM, CodeGenOpt::Level OL);
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FunctionPass *createPPCTLSDynamicCallPass();
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FunctionPass *createPPCBoolRetToIntPass();
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FunctionPass *createPPCExpandISELPass();
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@ -114,8 +114,8 @@ namespace {
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unsigned GlobalBaseReg;
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public:
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explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
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: SelectionDAGISel(tm), TM(tm) {}
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explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(tm, OptLevel), TM(tm) {}
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bool runOnMachineFunction(MachineFunction &MF) override {
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// Make sure we re-emit a set of the global base reg if necessary
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@ -5116,6 +5116,7 @@ void PPCDAGToDAGISel::PeepholePPC64() {
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/// createPPCISelDag - This pass converts a legalized DAG into a
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/// PowerPC-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
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return new PPCDAGToDAGISel(TM);
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FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM,
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CodeGenOpt::Level OptLevel) {
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return new PPCDAGToDAGISel(TM, OptLevel);
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}
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@ -352,7 +352,7 @@ bool PPCPassConfig::addILPOpts() {
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bool PPCPassConfig::addInstSelector() {
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// Install an instruction selector.
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addPass(createPPCISelDag(getPPCTargetMachine()));
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addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
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#ifndef NDEBUG
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if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
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@ -22,7 +22,7 @@ unequal:
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; CHECK-LABEL: func1:
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; CHECK: cmpld {{([0-9]+,)?}}4, 5
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; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]]
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; CHECK-DAG: std 3, -[[OFFSET1:[0-9]+]]
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; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]]
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; CHECK: ld 3, -[[OFFSET1]](1)
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; CHECK: ld 3, -[[OFFSET2]](1)
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@ -31,19 +31,19 @@ unequal:
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; DARWIN32: mr
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; DARWIN32: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]]
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; DARWIN32: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]]
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; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REGA]], r[[REGB]]
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; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REGB]], r[[REGA]]
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; DARWIN32: stw r[[REG1]], -[[OFFSET1:[0-9]+]]
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; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
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; DARWIN32: lwz r3, -[[OFFSET1]]
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; DARWIN32: lwz r3, -[[OFFSET2]]
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; DARWIN32: lwz r3, -[[OFFSET1]]
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; DARWIN64: _func1:
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; DARWIN64: mr
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; DARWIN64: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]]
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; DARWIN64: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]]
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; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGA]], r[[REGB]]
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; DARWIN64: std r[[REG1]], -[[OFFSET1:[0-9]+]]
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; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]]
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; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGB]], r[[REGA]]
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; DARWIN64: std r[[REG1]], -[[OFFSET2:[0-9]+]]
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; DARWIN64: std r[[REG2]], -[[OFFSET1:[0-9]+]]
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; DARWIN64: ld r3, -[[OFFSET1]]
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; DARWIN64: ld r3, -[[OFFSET2]]
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@ -61,19 +61,19 @@ unequal:
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ret i8* %array2_ptr
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}
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; CHECK-LABEL: func2:
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; CHECK: cmpld {{([0-9]+,)?}}4, 6
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; CHECK-DAG: cmpld {{([0-9]+,)?}}4, 6
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; CHECK-DAG: std 6, 72(1)
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; CHECK-DAG: std 5, 64(1)
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; CHECK-DAG: std 6, -[[OFFSET1:[0-9]+]]
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; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]]
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; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]]
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; CHECK: ld 3, -[[OFFSET2]](1)
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; CHECK: ld 3, -[[OFFSET1]](1)
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; DARWIN32-LABEL: _func2
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; DARWIN32-DAG: addi r[[REG8:[0-9]+]], r[[REGSP:[0-9]+]], 36
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; DARWIN32-DAG: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]])
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; DARWIN32: mr
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; DARWIN32: addi r[[REG8:[0-9]+]], r[[REGSP:[0-9]+]], 36
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; DARWIN32: mr r[[REG7:[0-9]+]], r5
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; DARWIN32: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]])
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; DARWIN32-DAG: cmplw {{(cr[0-9]+,)?}}r5, r[[REG2]]
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; DARWIN32-DAG: stw r[[REG7]], -[[OFFSET1:[0-9]+]]
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; DARWIN32-DAG: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
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@ -82,9 +82,9 @@ unequal:
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; DARWIN64: _func2:
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; DARWIN64: ld r[[REG2:[0-9]+]], 72(r1)
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; DARWIN64: mr
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; DARWIN64: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]]
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; DARWIN64: ld r[[REG2:[0-9]+]], 72(r1)
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; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGA]], r[[REG2]]
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; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]]
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; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]]
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@ -107,9 +107,9 @@ unequal:
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}
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; CHECK-LABEL: func3:
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; CHECK: cmpld {{([0-9]+,)?}}4, 6
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; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]](1)
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; CHECK-DAG: std 6, -[[OFFSET1:[0-9]+]](1)
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; CHECK-DAG: cmpld {{([0-9]+,)?}}3, 4
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; CHECK-DAG: std 3, -[[OFFSET2:[0-9]+]](1)
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; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]](1)
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; CHECK: ld 3, -[[OFFSET2]](1)
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; CHECK: ld 3, -[[OFFSET1]](1)
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@ -127,13 +127,13 @@ unequal:
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; DARWIN32-DAG: lwz r3, -[[OFFSET2:[0-9]+]]
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; DARWIN64: _func3:
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; DARWIN64: ld r[[REG3:[0-9]+]], 72(r1)
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; DARWIN64: ld r[[REG4:[0-9]+]], 56(r1)
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; DARWIN64-DAG: ld r[[REG3:[0-9]+]], 72(r1)
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; DARWIN64-DAG: ld r[[REG4:[0-9]+]], 56(r1)
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; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]]
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; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]]
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; DARWIN64: std r[[REG4]], -[[OFFSET2:[0-9]+]]
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; DARWIN64: ld r3, -[[OFFSET2]]
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; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]]
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; DARWIN64: std r[[REG3]], -[[OFFSET2:[0-9]+]]
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; DARWIN64: ld r3, -[[OFFSET1]]
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; DARWIN64: ld r3, -[[OFFSET2]]
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define i8* @func4(i64 %p1, i64 %p2, i64 %p3, i64 %p4,
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@ -152,31 +152,31 @@ unequal:
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}
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; CHECK-LABEL: func4:
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; CHECK: ld [[REG3:[0-9]+]], 136(1)
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; CHECK: ld [[REG2:[0-9]+]], 120(1)
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; CHECK: cmpld {{([0-9]+,)?}}[[REG2]], [[REG3]]
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; CHECK: std [[REG3]], -[[OFFSET2:[0-9]+]](1)
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; CHECK-DAG: ld [[REG2:[0-9]+]], 120(1)
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; CHECK-DAG: ld [[REG3:[0-9]+]], 136(1)
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; CHECK-DAG: cmpld {{([0-9]+,)?}}[[REG2]], [[REG3]]
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; CHECK: std [[REG2]], -[[OFFSET1:[0-9]+]](1)
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; CHECK: std [[REG3]], -[[OFFSET2:[0-9]+]](1)
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; CHECK: ld 3, -[[OFFSET1]](1)
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; CHECK: ld 3, -[[OFFSET2]](1)
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; DARWIN32: _func4:
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; DARWIN32: lwz r[[REG4:[0-9]+]], 96(r1)
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; DARWIN32: addi r[[REG1:[0-9]+]], r1, 100
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; DARWIN32: lwz r[[REG3:[0-9]+]], 108(r1)
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; DARWIN32: mr r[[REG2:[0-9]+]], r[[REG4]]
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; DARWIN32: lwz r[[REG3:[0-9]+]], 108(r1)
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; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]]
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; DARWIN32: stw r[[REG2]], -[[OFFSET1:[0-9]+]]
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; DARWIN32: stw r[[REG3]], -[[OFFSET2:[0-9]+]]
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; DARWIN32: lwz r[[REG1]], -[[OFFSET1]]
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; DARWIN32: lwz r[[REG1]], -[[OFFSET2]]
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; DARWIN32-DAG: stw r[[REG2]], -[[OFFSET1:[0-9]+]]
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; DARWIN32-DAG: stw r[[REG3]], -[[OFFSET2:[0-9]+]]
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; DARWIN32: lwz r3, -[[OFFSET1]]
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; DARWIN32: lwz r3, -[[OFFSET2]]
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; DARWIN64: _func4:
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; DARWIN64: ld r[[REG2:[0-9]+]], 120(r1)
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; DARWIN64: ld r[[REG3:[0-9]+]], 136(r1)
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; DARWIN64: mr r[[REG4:[0-9]+]], r[[REG2]]
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; DARWIN64-DAG: ld r[[REG3:[0-9]+]], 136(r1)
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; DARWIN64-DAG: mr r[[REG4:[0-9]+]], r[[REG2]]
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; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REG2]], r[[REG3]]
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; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]]
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; DARWIN64: std r[[REG3]], -[[OFFSET2:[0-9]+]]
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; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]]
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; DARWIN64: ld r3, -[[OFFSET1]]
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; DARWIN64: ld r3, -[[OFFSET2]]
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@ -1,4 +1,4 @@
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; RUN: llc -verify-machineinstrs -O0 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -O2 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s
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; This verifies that single-precision floating point values that can't
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; be passed in registers are stored in the rightmost word of the parameter
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@ -1,6 +1,6 @@
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -fast-isel=false -mattr=-vsx < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-P9 %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O2 -fast-isel=false -mattr=-vsx < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O2 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O2 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-P9 %s
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; Verify internal alignment of long double in a struct. The double
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; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain
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@ -44,9 +44,9 @@ entry:
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; CHECK-VSX-DAG: std 3, 48(1)
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; CHECK-VSX-DAG: std 5, -16(1)
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; CHECK-VSX-DAG: std 6, -8(1)
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; CHECK-VSX: addi 3, 1, -16
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; CHECK-VSX: lxsdx 1, 0, 3
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; CHECK-VSX: addi 3, 1, -8
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; CHECK-VSX-DAG: addi [[REG1:[0-9]+]], 1, -16
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; CHECK-VSX-DAG: addi 3, 1, -8
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; CHECK-VSX: lxsdx 1, 0, [[REG1]]
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; CHECK-VSX: lxsdx 2, 0, 3
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; FIXME-VSX: addi 4, 1, 48
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@ -54,9 +54,9 @@ entry:
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; FIXME-VSX: li 3, 24
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; FIXME-VSX: lxsdx 2, 4, 3
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; CHECK-P9: std 6, 72(1)
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; CHECK-P9: std 5, 64(1)
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; CHECK-P9: std 4, 56(1)
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; CHECK-P9: std 3, 48(1)
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; CHECK-P9: mtvsrd 1, 5
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; CHECK-P9: mtvsrd 2, 6
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; CHECK-P9-DAG: std 6, 72(1)
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; CHECK-P9-DAG: std 5, 64(1)
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; CHECK-P9-DAG: std 4, 56(1)
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; CHECK-P9-DAG: std 3, 48(1)
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; CHECK-P9-DAG: mtvsrd 1, 5
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; CHECK-P9-DAG: mtvsrd 2, 6
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@ -11,8 +11,8 @@ target triple = "powerpc64-unknown-linux-gnu"
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define i32 @localexec() nounwind {
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entry:
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;OPT0: addis [[REG1:[0-9]+]], 13, a@tprel@ha
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;OPT0-NEXT: li [[REG2:[0-9]+]], 42
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;OPT0-NEXT: addi [[REG1]], [[REG1]], a@tprel@l
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;OPT0-NEXT: li [[REG2:[0-9]+]], 42
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;OPT0: stw [[REG2]], 0([[REG1]])
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;OPT1: addis [[REG1:[0-9]+]], 13, a@tprel@ha
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;OPT1-NEXT: li [[REG2:[0-9]+]], 42
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