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[Legalizer] Add support for G_OR NarrowScalar.
Legalize bitwise OR: A = BinOp<Ty> B, C into: B1, ..., BN = G_UNMERGE_VALUES B C1, ..., CN = G_UNMERGE_VALUES C A1 = BinOp<Ty/N> B1, C2 ... AN = BinOp<Ty/N> BN, CN A = G_MERGE_VALUES A1, ..., AN llvm-svn: 314760
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@ -396,6 +396,50 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_OR: {
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// Legalize bitwise operation:
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// A = BinOp<Ty> B, C
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// into:
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// B1, ..., BN = G_UNMERGE_VALUES B
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// C1, ..., CN = G_UNMERGE_VALUES C
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// A1 = BinOp<Ty/N> B1, C2
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// ...
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// AN = BinOp<Ty/N> BN, CN
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// A = G_MERGE_VALUES A1, ..., AN
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unsigned NarrowSize = NarrowTy.getSizeInBits();
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int NumParts =
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MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
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// List the registers where the destination will be scattered.
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SmallVector<unsigned, 2> DstRegs;
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// List the registers where the first argument will be split.
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SmallVector<unsigned, 2> SrcsReg1;
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// List the registers where the second argument will be split.
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SmallVector<unsigned, 2> SrcsReg2;
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// Create all the temporary registers.
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for (int i = 0; i < NumParts; ++i) {
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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unsigned SrcReg1 = MRI.createGenericVirtualRegister(NarrowTy);
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unsigned SrcReg2 = MRI.createGenericVirtualRegister(NarrowTy);
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DstRegs.push_back(DstReg);
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SrcsReg1.push_back(SrcReg1);
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SrcsReg2.push_back(SrcReg2);
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}
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// Explode the big arguments into smaller chunks.
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MIRBuilder.buildUnmerge(SrcsReg1, MI.getOperand(1).getReg());
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MIRBuilder.buildUnmerge(SrcsReg2, MI.getOperand(2).getReg());
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// Do the operation on each small part.
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for (int i = 0; i < NumParts; ++i)
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MIRBuilder.buildOr(DstRegs[i], SrcsReg1[i], SrcsReg2[i]);
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// Gather the destination registers into the final destination.
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unsigned DstReg = MI.getOperand(0).getReg();
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MIRBuilder.buildMerge(DstReg, DstRegs);
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MI.eraseFromParent();
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return Legalized;
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}
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}
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}
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@ -48,6 +48,7 @@ LegalizerInfo::LegalizerInfo() {
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DefaultActions[TargetOpcode::G_ADD] = NarrowScalar;
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DefaultActions[TargetOpcode::G_LOAD] = NarrowScalar;
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DefaultActions[TargetOpcode::G_STORE] = NarrowScalar;
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DefaultActions[TargetOpcode::G_OR] = NarrowScalar;
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DefaultActions[TargetOpcode::G_BRCOND] = WidenScalar;
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DefaultActions[TargetOpcode::G_INSERT] = NarrowScalar;
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@ -1,13 +1,4 @@
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# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--"
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define void @test_scalar_or_small() {
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entry:
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ret void
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}
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...
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# RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=legalizer -global-isel %s -o - | FileCheck %s
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---
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name: test_scalar_or_small
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@ -19,7 +10,7 @@ registers:
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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body: |
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bb.0.entry:
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bb.0:
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liveins: %x0, %x1, %x2, %x3
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; CHECK-LABEL: name: test_scalar_or_small
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; CHECK: [[OP0:%.*]](s32) = G_TRUNC %0
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@ -35,3 +26,49 @@ body: |
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%5(s64) = G_ANYEXT %2
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%x0 = COPY %5
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...
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---
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name: test_big_scalar_power_of_2
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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- { id: 7, class: _ }
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- { id: 8, class: _ }
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body: |
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bb.0:
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liveins: %x0, %x1, %x2, %x3
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; CHECK-LABEL: name: test_big_scalar_power_of_2
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; CHECK: [[OP0_0:%.*]](s64) = COPY %x0
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; CHECK-NEXT: [[OP0_1:%.*]](s64) = COPY %x1
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; CHECK-NEXT: [[OP1_0:%.*]](s64) = COPY %x2
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; CHECK-NEXT: [[OP1_1:%.*]](s64) = COPY %x3
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; CHECK-NEXT: [[RES_0:%.*]](s64) = G_OR [[OP0_0]], [[OP1_0]]
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; CHECK-NEXT: [[RES_1:%.*]](s64) = G_OR [[OP0_1]], [[OP1_1]]
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; We have a temporary G_MERGE_VALUES in the legalizer
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; that gets cleaned up with the G_UNMERGE_VALUES.
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; Thus,
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; tmp = G_MERGE_VALUES [[RES_0]], [[RES_1]]
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; %7, %8 = G_UNMERGE_VALUES tmp
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; %x0 = COPY %7
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; %x1 = COPY %8
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; translates into
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; CHECK-NEXT: %x0 = COPY [[RES_0]]
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; CHECK-NEXT: %x1 = COPY [[RES_1]]
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%0(s64) = COPY %x0
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%1(s64) = COPY %x1
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%2(s64) = COPY %x2
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%3(s64) = COPY %x3
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%4(s128) = G_MERGE_VALUES %0, %1
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%5(s128) = G_MERGE_VALUES %2, %3
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%6(s128) = G_OR %4, %5
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%7(s64), %8(s64) = G_UNMERGE_VALUES %6
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%x0 = COPY %7
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%x1 = COPY %8
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RET_ReallyLR implicit %x0, implicit %x1
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...
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