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[mips] Add microMIPSR6 ll/sc instructions.

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Previously the compiler was using the microMIPSR3 variants, incorrectly.

Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D46948

llvm-svn: 332820
This commit is contained in:
Simon Dardis 2018-05-20 17:21:00 +00:00
parent 9be56b15fd
commit 69c7283859
10 changed files with 82 additions and 15 deletions
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2
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
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@ -1860,7 +1860,7 @@ static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
if (Inst.getOpcode() == Mips::SCE_MM)
if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Reg));

18
lib/Target/Mips/MicroMips32r6InstrFormats.td
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@ -1032,3 +1032,21 @@ class POOL32B_LDWC2_SDWC2_FM_MMR6<string instr_asm, bits<4> funct>
let Inst{11} = 0;
let Inst{10-0} = offset;
}
class POOL32C_LL_E_SC_E_FM_MMR6<string instr_asm, bits<4> majorFunc,
bits<3> minorFunc>
: MMR6Arch<instr_asm>, MipsR6Inst {
bits<5> rt;
bits<21> addr;
bits<5> base = addr{20-16};
bits<9> offset = addr{8-0};
bits<32> Inst;
let Inst{31-26} = 0b011000;
let Inst{25-21} = rt;
let Inst{20-16} = base;
let Inst{15-12} = majorFunc;
let Inst{11-9} = minorFunc;
let Inst{8-0} = offset;
}

29
lib/Target/Mips/MicroMips32r6InstrInfo.td
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@ -234,6 +234,9 @@ class SDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"sdc2", 0b1010>;
class LWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"lwc2", 0b0000>;
class SWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"swc2", 0b1000>;
class LL_MMR6_ENC : POOL32C_LL_E_SC_E_FM_MMR6<"ll", 0b0011, 0b000>;
class SC_MMR6_ENC : POOL32C_LL_E_SC_E_FM_MMR6<"sc", 0b1011, 0b000>;
/// Floating Point Instructions
class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
@ -847,6 +850,30 @@ class GINVI_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvi", GPR32Opnd,
class GINVT_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvt", GPR32Opnd,
II_GINVT>;
class SC_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
dag OutOperandList = (outs GPR32Opnd:$dst);
dag InOperandList = (ins GPR32Opnd:$rt, mem_mm_9:$addr);
string AsmString = !strconcat(opstr, "\t$rt, $addr");
InstrItinClass Itinerary = itin;
string BaseOpcode = opstr;
bit mayStore = 1;
string Constraints = "$rt = $dst";
string DecoderMethod = "DecodeMemMMImm9";
}
class LL_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
dag OutOperandList = (outs GPR32Opnd:$rt);
dag InOperandList = (ins mem_mm_9:$addr);
string AsmString = !strconcat(opstr, "\t$rt, $addr");
InstrItinClass Itinerary = itin;
string BaseOpcode = opstr;
bit mayLoad = 1;
string DecoderMethod = "DecodeMemMMImm9";
}
class SC_MMR6_DESC : SC_MMR6_DESC_BASE<"sc", II_SC>;
class LL_MMR6_DESC : LL_MMR6_DESC_BASE<"ll", II_LL>;
/// Floating Point Instructions
class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
InstrItinClass Itin, bit isComm,
@ -1593,6 +1620,8 @@ def LDC2_MMR6 : StdMMR6Rel, LDC2_MMR6_ENC, LDC2_MMR6_DESC, ISA_MICROMIPS32R6;
def SDC2_MMR6 : StdMMR6Rel, SDC2_MMR6_ENC, SDC2_MMR6_DESC, ISA_MICROMIPS32R6;
def LWC2_MMR6 : StdMMR6Rel, LWC2_MMR6_ENC, LWC2_MMR6_DESC, ISA_MICROMIPS32R6;
def SWC2_MMR6 : StdMMR6Rel, SWC2_MMR6_ENC, SWC2_MMR6_DESC, ISA_MICROMIPS32R6;
def LL_MMR6 : R6MMR6Rel, LL_MMR6_ENC, LL_MMR6_DESC, ISA_MICROMIPS32R6;
def SC_MMR6 : R6MMR6Rel, SC_MMR6_ENC, SC_MMR6_DESC, ISA_MICROMIPS32R6;
}
def BOVC_MMR6 : R6MMR6Rel, BOVC_MMR6_ENC, BOVC_MMR6_DESC, ISA_MICROMIPS32R6,

12
lib/Target/Mips/MicroMipsInstrInfo.td
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@ -1041,13 +1041,13 @@ let DecoderNamespace = "MicroMips" in {
TEQI_FM_MM<0x0a>, ISA_MICROMIPS32_NOT_MIPS32R6;
def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM_MM<0x0c>,
ISA_MICROMIPS32_NOT_MIPS32R6;
}
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
/// Load-linked, Store-conditional
def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
}
let DecoderNamespace = "MicroMips" in {
def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def LLE_MM : MMRel, LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>,
ISA_MICROMIPS, ASE_EVA;
def SCE_MM : MMRel, SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>,

16
lib/Target/Mips/MipsISelLowering.cpp
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@ -1433,8 +1433,8 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
if (Size == 4) {
if (isMicroMips) {
LL = Mips::LL_MM;
SC = Mips::SC_MM;
LL = Subtarget.hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM;
SC = Subtarget.hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM;
} else {
LL = Subtarget.hasMips32r6()
? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
@ -1580,8 +1580,8 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
unsigned LL, SC;
if (isMicroMips) {
LL = Mips::LL_MM;
SC = Mips::SC_MM;
LL = Subtarget.hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM;
SC = Subtarget.hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM;
} else {
LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
: (ArePtrs64bit ? Mips::LL64 : Mips::LL);
@ -1721,8 +1721,8 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
if (Size == 4) {
if (isMicroMips) {
LL = Mips::LL_MM;
SC = Mips::SC_MM;
LL = Subtarget.hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM;
SC = Subtarget.hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM;
} else {
LL = Subtarget.hasMips32r6()
? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
@ -1835,8 +1835,8 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
unsigned LL, SC;
if (isMicroMips) {
LL = Mips::LL_MM;
SC = Mips::SC_MM;
LL = Subtarget.hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM;
SC = Subtarget.hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM;
} else {
LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
: (ArePtrs64bit ? Mips::LL64 : Mips::LL);

2
lib/Target/Mips/MipsSERegisterInfo.cpp
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@ -98,6 +98,8 @@ static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode,
case Mips::SC64_R6:
case Mips::SCD_R6:
case Mips::SC_R6:
case Mips::LL_MMR6:
case Mips::SC_MMR6:
return 9;
case Mips::INLINEASM: {
unsigned ConstraintID = InlineAsm::getMemoryConstraintID(MO.getImm());

4
test/MC/Disassembler/Mips/micromips32r6/valid.txt
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@ -351,3 +351,7 @@
0xf4 0x40 0x00 0x40 # CHECK: blezc $2, 260
0xf6 0x10 0x00 0x80 # CHECK: bgezc $16, 516
0xd5 0x80 0x01 0x00 # CHECK: bgtzc $12, 1028
0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4)
0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4)
0x60 0x44 0x6c 0x08 # CHECK: lle $2, 8($4)
0x60 0x44 0xac 0x08 # CHECK: sce $2, 8($4)

4
test/MC/Mips/micromips32r6/invalid-wrong-error.s
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@ -24,3 +24,7 @@
swc2 $1, 2048($17) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
lwc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
lwc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sc $4, 512($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
sc $4, -513($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
ll $4, 512($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
ll $4, -513($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled

8
test/MC/Mips/micromips32r6/invalid.s
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@ -154,6 +154,10 @@
sra $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
srl $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
srl $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
ll $33, 8($5) # CHECK: :[[@LINE]]:6: error: invalid register number
ll $4, 8($33) # CHECK: :[[@LINE]]:12: error: invalid register number
ll $4, 512($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
ll $4, -513($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
lle $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number
lle $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number
lle $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
@ -166,6 +170,10 @@
sbe $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number
sbe $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
sbe $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
sc $33, 8($5) # CHECK: :[[@LINE]]:6: error: invalid register number
sc $4, 8($33) # CHECK: :[[@LINE]]:12: error: invalid register number
sc $4, 512($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
sc $4, -513($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
sce $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number
sce $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number
sce $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset

2
test/MC/Mips/micromips32r6/valid.s
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@ -74,6 +74,7 @@
lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08]
# CHECK-NEXT: # <MCInst #{{.*}} LL_MMR6
lwm32 $16, $17, 8($4) # CHECK: lwm32 $16, $17, 8($4) # encoding: [0x20,0x44,0x50,0x08]
lwm32 $16, $17, 8($sp) # CHECK: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08]
lwm32 $16, $17, $ra, 8($4) # CHECK: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08]
@ -88,6 +89,7 @@
rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08]
# CHECK-NEXT: # <MCInst #{{.*}} SC_MMR6
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xa6,0x23,0x50]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xa6,0x23,0x90]
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0x85,0x20,0x10]