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Fix assert in X86 backend.

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When running combine on an extract_vector_elt, it wants to look through
a bitcast to check if the argument to the bitcast was itself an
extract_vector_elt with particular operands.

However, it called getOperand() on the argument to the bitcast *before*
checking that the opcode was EXTRACT_VECTOR_ELT, assert-failing if there
were zero operands for the actual opcode.

Fix, and add trivial test.

llvm-svn: 249891
This commit is contained in:
James Y Knight 2015-10-09 20:10:14 +00:00
parent 432874b47f
commit 6a7b902bbf
2 changed files with 14 additions and 8 deletions
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16
lib/Target/X86/X86ISelLowering.cpp
View File

@ -22913,15 +22913,15 @@ static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
InputVector.getNode()->getOperand(0));
// The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
SDValue MMXSrcOp = MMXSrc.getOperand(0);
if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
MMXSrcOp.getOpcode() == ISD::BITCAST &&
MMXSrcOp.getValueType() == MVT::v1i64 &&
MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
N->getValueType(0),
MMXSrcOp.getOperand(0));
MMXSrc.getValueType() == MVT::i64) {
SDValue MMXSrcOp = MMXSrc.getOperand(0);
if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
MMXSrcOp.getValueType() == MVT::v1i64 &&
MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
N->getValueType(0), MMXSrcOp.getOperand(0));
}
}
EVT VT = N->getValueType(0);

6
test/CodeGen/Generic/vector.ll
View File

@ -156,3 +156,9 @@ define <2 x i32*> @vector_gep(<2 x [3 x {i32, i32}]*> %a) {
%w = getelementptr [3 x {i32, i32}], <2 x [3 x {i32, i32}]*> %a, <2 x i32> <i32 1, i32 2>, <2 x i32> <i32 2, i32 3>, <2 x i32> <i32 1, i32 1>
ret <2 x i32*> %w
}
define i32 @extractelt_constant_bitcast() {
%1 = bitcast i64 4 to <2 x i32>
%2 = extractelement <2 x i32> %1, i32 0
ret i32 %2
}