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Fix thinko
llvm-svn: 75957
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@ -119,26 +119,24 @@ def F15 : FPR<15, "f15">, DwarfRegNum<[31]>;
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def PSW : SystemZReg<"psw">;
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def subreg_32bit : PatLeaf<(i32 1)>;
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def subreg_64even : PatLeaf<(i32 2)>;
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def subreg_64odd : PatLeaf<(i32 3)>;
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def subreg_32even : PatLeaf<(i32 4)>;
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def subreg_32odd : PatLeaf<(i32 5)>;
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def subreg_even : PatLeaf<(i32 1)>;
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def subreg_odd : PatLeaf<(i32 2)>;
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def : SubRegSet<1, [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D,
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R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
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[R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W,
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R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
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def : SubRegSet<2, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
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def : SubRegSet<1, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
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[R0D, R2D, R4D, R6D, R8D, R10D, R12D, R14D]>;
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def : SubRegSet<3, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
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def : SubRegSet<2, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
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[R1D, R3D, R5D, R7D, R9D, R11D, R13D, R15D]>;
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def : SubRegSet<4, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
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def : SubRegSet<1, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
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[R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>;
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def : SubRegSet<5, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
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def : SubRegSet<2, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
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[R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>;
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/// Register classes
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