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Detecte vector reduction operations just before instruction selection.
(This is the second attemp to commit this patch, after fixing pr26652 & pr26653). This patch detects vector reductions before instruction selection. Vector reductions are vectorized reduction operations, and for such operations we have freedom to reorganize the elements of the result as long as the reduction of them stay unchanged. This will enable some reduction pattern recognition during instruction combine such as SAD/dot-product on X86. A flag is added to SDNodeFlags to mark those vector reduction nodes to be checked during instruction combine. To detect those vector reductions, we search def-use chains starting from the given instruction, and check if all uses fall into two categories: 1. Reduction with another vector. 2. Reduction on all elements. in which 2 is detected by recognizing the pattern that the loop vectorizer generates to reduce all elements in the vector outside of the loop, which includes several ShuffleVector and one ExtractElement instructions. Differential revision: http://reviews.llvm.org/D15250 llvm-svn: 261804
This commit is contained in:
Cong Hou
parent
234a2e7455
commit
6af13323da
@ -328,6 +328,7 @@ private:
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bool NoInfs : 1;
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bool NoSignedZeros : 1;
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bool AllowReciprocal : 1;
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bool VectorReduction : 1;
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public:
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/// Default constructor turns off all optimization flags.
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@ -340,6 +341,7 @@ public:
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NoInfs = false;
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NoSignedZeros = false;
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AllowReciprocal = false;
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VectorReduction = false;
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}
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// These are mutators for each flag.
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@ -351,6 +353,7 @@ public:
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void setNoInfs(bool b) { NoInfs = b; }
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void setNoSignedZeros(bool b) { NoSignedZeros = b; }
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void setAllowReciprocal(bool b) { AllowReciprocal = b; }
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void setVectorReduction(bool b) { VectorReduction = b; }
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// These are accessors for each flag.
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bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
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@ -361,6 +364,7 @@ public:
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bool hasNoInfs() const { return NoInfs; }
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bool hasNoSignedZeros() const { return NoSignedZeros; }
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bool hasAllowReciprocal() const { return AllowReciprocal; }
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bool hasVectorReduction() const { return VectorReduction; }
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/// Return a raw encoding of the flags.
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/// This function should only be used to add data to the NodeID value.
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@ -2317,6 +2317,129 @@ void SelectionDAGBuilder::visitFSub(const User &I) {
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visitBinary(I, ISD::FSUB);
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}
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/// Checks if the given instruction performs a vector reduction, in which case
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/// we have the freedom to alter the elements in the result as long as the
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/// reduction of them stays unchanged.
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static bool isVectorReductionOp(const User *I) {
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const Instruction *Inst = dyn_cast<Instruction>(I);
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if (!Inst || !Inst->getType()->isVectorTy())
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return false;
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auto OpCode = Inst->getOpcode();
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switch (OpCode) {
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case Instruction::Add:
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case Instruction::Mul:
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case Instruction::And:
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case Instruction::Or:
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case Instruction::Xor:
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break;
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case Instruction::FAdd:
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case Instruction::FMul:
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if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst))
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if (FPOp->getFastMathFlags().unsafeAlgebra())
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break;
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// Fall through.
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default:
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return false;
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}
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unsigned ElemNum = Inst->getType()->getVectorNumElements();
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unsigned ElemNumToReduce = ElemNum;
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// Do DFS search on the def-use chain from the given instruction. We only
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// allow four kinds of operations during the search until we reach the
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// instruction that extracts the first element from the vector:
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//
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// 1. The reduction operation of the same opcode as the given instruction.
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//
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// 2. PHI node.
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//
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// 3. ShuffleVector instruction together with a reduction operation that
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// does a partial reduction.
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//
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// 4. ExtractElement that extracts the first element from the vector, and we
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// stop searching the def-use chain here.
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//
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// 3 & 4 above perform a reduction on all elements of the vector. We push defs
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// from 1-3 to the stack to continue the DFS. The given instruction is not
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// a reduction operation if we meet any other instructions other than those
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// listed above.
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SmallVector<const User *, 16> UsersToVisit{Inst};
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SmallPtrSet<const User *, 16> Visited;
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bool ReduxExtracted = false;
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while (!UsersToVisit.empty()) {
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auto User = UsersToVisit.back();
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UsersToVisit.pop_back();
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if (!Visited.insert(User).second)
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continue;
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for (const auto &U : User->users()) {
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auto Inst = dyn_cast<Instruction>(U);
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if (!Inst)
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return false;
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if (Inst->getOpcode() == OpCode || isa<PHINode>(U)) {
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if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst))
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if (!isa<PHINode>(FPOp) && !FPOp->getFastMathFlags().unsafeAlgebra())
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return false;
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UsersToVisit.push_back(U);
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} else if (const ShuffleVectorInst *ShufInst =
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dyn_cast<ShuffleVectorInst>(U)) {
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// Detect the following pattern: A ShuffleVector instruction together
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// with a reduction that do partial reduction on the first and second
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// ElemNumToReduce / 2 elements, and store the result in
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// ElemNumToReduce / 2 elements in another vector.
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unsigned ResultElements = ShufInst->getType()->getVectorNumElements();
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ElemNumToReduce = ResultElements <= ElemNumToReduce ? ResultElements
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: ElemNumToReduce;
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if (ElemNumToReduce == 1)
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return false;
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if (!isa<UndefValue>(U->getOperand(1)))
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return false;
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for (unsigned i = 0; i < ElemNumToReduce / 2; ++i)
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if (ShufInst->getMaskValue(i) != int(i + ElemNumToReduce / 2))
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return false;
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for (unsigned i = ElemNumToReduce / 2; i < ElemNum; ++i)
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if (ShufInst->getMaskValue(i) != -1)
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return false;
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// There is only one user of this ShuffleVector instruction, which
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// must
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// be a reduction operation.
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if (!U->hasOneUse())
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return false;
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auto U2 = dyn_cast<Instruction>(*U->user_begin());
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if (!U2 || U2->getOpcode() != OpCode)
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return false;
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// Check operands of the reduction operation.
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if ((U2->getOperand(0) == U->getOperand(0) && U2->getOperand(1) == U) ||
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(U2->getOperand(1) == U->getOperand(0) && U2->getOperand(0) == U)) {
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UsersToVisit.push_back(U2);
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ElemNumToReduce /= 2;
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} else
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return false;
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} else if (isa<ExtractElementInst>(U)) {
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// At this moment we should have reduced all elements in the vector.
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if (ElemNumToReduce != 1)
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return false;
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const ConstantInt *Val = dyn_cast<ConstantInt>(U->getOperand(1));
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if (!Val || Val->getZExtValue() != 0)
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return false;
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ReduxExtracted = true;
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} else
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return false;
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}
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}
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return ReduxExtracted;
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}
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void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
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SDValue Op1 = getValue(I.getOperand(0));
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SDValue Op2 = getValue(I.getOperand(1));
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@ -2324,6 +2447,7 @@ void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
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bool nuw = false;
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bool nsw = false;
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bool exact = false;
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bool vec_redux = false;
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FastMathFlags FMF;
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if (const OverflowingBinaryOperator *OFBinOp =
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@ -2337,10 +2461,16 @@ void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
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if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
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FMF = FPOp->getFastMathFlags();
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if (isVectorReductionOp(&I)) {
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vec_redux = true;
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DEBUG(dbgs() << "Detected a reduction operation:" << I << "\n");
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}
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SDNodeFlags Flags;
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Flags.setExact(exact);
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Flags.setNoSignedWrap(nsw);
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Flags.setNoUnsignedWrap(nuw);
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Flags.setVectorReduction(vec_redux);
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if (EnableFMFInDAG) {
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Flags.setAllowReciprocal(FMF.allowReciprocal());
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Flags.setNoInfs(FMF.noInfs());
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8
test/CodeGen/Generic/pr26652.ll
Normal file
8
test/CodeGen/Generic/pr26652.ll
Normal file
@ -0,0 +1,8 @@
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; RUN: llc < %s
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define <2 x i32> @test(<4 x i32> %a, <4 x i32> %b) {
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entry:
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%0 = or <4 x i32> %a, %b
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%1 = shufflevector <4 x i32> %0, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
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ret <2 x i32> %1
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}
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237
test/CodeGen/Generic/vector-redux.ll
Normal file
237
test/CodeGen/Generic/vector-redux.ll
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@ -0,0 +1,237 @@
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; RUN: llc < %s -debug-only=isel -o /dev/null 2>&1 | FileCheck %s
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; REQUIRES: asserts
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@a = global [1024 x i32] zeroinitializer, align 16
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define i32 @reduce_add() {
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; CHECK-LABEL: reduce_add
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; CHECK: Detected a reduction operation: {{.*}} add
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; CHECK: Detected a reduction operation: {{.*}} add
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; CHECK: Detected a reduction operation: {{.*}} add
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; CHECK: Detected a reduction operation: {{.*}} add
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; CHECK: Detected a reduction operation: {{.*}} add
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; CHECK: Detected a reduction operation: {{.*}} add
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; CHECK: Detected a reduction operation: {{.*}} add
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; CHECK: Detected a reduction operation: {{.*}} add
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; CHECK: Detected a reduction operation: {{.*}} add
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; CHECK: Detected a reduction operation: {{.*}} add
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; CHECK: Detected a reduction operation: {{.*}} add
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min.iters.checked:
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br label %vector.body
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vector.body:
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%index = phi i64 [ 0, %min.iters.checked ], [ %index.next.4, %vector.body ]
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%vec.phi = phi <4 x i32> [ zeroinitializer, %min.iters.checked ], [ %28, %vector.body ]
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%vec.phi4 = phi <4 x i32> [ zeroinitializer, %min.iters.checked ], [ %29, %vector.body ]
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%0 = getelementptr inbounds [1024 x i32], [1024 x i32]* @a, i64 0, i64 %index
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%1 = bitcast i32* %0 to <4 x i32>*
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%wide.load = load <4 x i32>, <4 x i32>* %1, align 16
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%2 = getelementptr i32, i32* %0, i64 4
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%3 = bitcast i32* %2 to <4 x i32>*
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%wide.load5 = load <4 x i32>, <4 x i32>* %3, align 16
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%4 = add nsw <4 x i32> %wide.load, %vec.phi
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%5 = add nsw <4 x i32> %wide.load5, %vec.phi4
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%index.next = add nuw nsw i64 %index, 8
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%6 = getelementptr inbounds [1024 x i32], [1024 x i32]* @a, i64 0, i64 %index.next
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%7 = bitcast i32* %6 to <4 x i32>*
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%wide.load.1 = load <4 x i32>, <4 x i32>* %7, align 16
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%8 = getelementptr i32, i32* %6, i64 4
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%9 = bitcast i32* %8 to <4 x i32>*
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%wide.load5.1 = load <4 x i32>, <4 x i32>* %9, align 16
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%10 = add nsw <4 x i32> %wide.load.1, %4
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%11 = add nsw <4 x i32> %wide.load5.1, %5
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%index.next.1 = add nsw i64 %index, 16
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%12 = getelementptr inbounds [1024 x i32], [1024 x i32]* @a, i64 0, i64 %index.next.1
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%13 = bitcast i32* %12 to <4 x i32>*
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%wide.load.2 = load <4 x i32>, <4 x i32>* %13, align 16
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%14 = getelementptr i32, i32* %12, i64 4
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%15 = bitcast i32* %14 to <4 x i32>*
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%wide.load5.2 = load <4 x i32>, <4 x i32>* %15, align 16
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%16 = add nsw <4 x i32> %wide.load.2, %10
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%17 = add nsw <4 x i32> %wide.load5.2, %11
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%index.next.2 = add nsw i64 %index, 24
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%18 = getelementptr inbounds [1024 x i32], [1024 x i32]* @a, i64 0, i64 %index.next.2
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%19 = bitcast i32* %18 to <4 x i32>*
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%wide.load.3 = load <4 x i32>, <4 x i32>* %19, align 16
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%20 = getelementptr i32, i32* %18, i64 4
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%21 = bitcast i32* %20 to <4 x i32>*
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%wide.load5.3 = load <4 x i32>, <4 x i32>* %21, align 16
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%22 = add nsw <4 x i32> %wide.load.3, %16
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%23 = add nsw <4 x i32> %wide.load5.3, %17
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%index.next.3 = add nsw i64 %index, 32
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%24 = getelementptr inbounds [1024 x i32], [1024 x i32]* @a, i64 0, i64 %index.next.3
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%25 = bitcast i32* %24 to <4 x i32>*
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%wide.load.4 = load <4 x i32>, <4 x i32>* %25, align 16
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%26 = getelementptr i32, i32* %24, i64 4
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%27 = bitcast i32* %26 to <4 x i32>*
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%wide.load5.4 = load <4 x i32>, <4 x i32>* %27, align 16
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%28 = add nsw <4 x i32> %wide.load.4, %22
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%29 = add nsw <4 x i32> %wide.load5.4, %23
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%index.next.4 = add nsw i64 %index, 40
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%30 = icmp eq i64 %index.next.4, 1000
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br i1 %30, label %middle.block, label %vector.body
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middle.block:
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%.lcssa10 = phi <4 x i32> [ %29, %vector.body ]
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%.lcssa = phi <4 x i32> [ %28, %vector.body ]
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%bin.rdx = add <4 x i32> %.lcssa10, %.lcssa
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%rdx.shuf = shufflevector <4 x i32> %bin.rdx, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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%bin.rdx6 = add <4 x i32> %bin.rdx, %rdx.shuf
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%rdx.shuf7 = shufflevector <4 x i32> %bin.rdx6, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%bin.rdx8 = add <4 x i32> %bin.rdx6, %rdx.shuf7
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%31 = extractelement <4 x i32> %bin.rdx8, i32 0
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ret i32 %31
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}
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define i32 @reduce_and() {
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; CHECK-LABEL: reduce_and
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; CHECK: Detected a reduction operation: {{.*}} and
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; CHECK: Detected a reduction operation: {{.*}} and
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; CHECK: Detected a reduction operation: {{.*}} and
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; CHECK: Detected a reduction operation: {{.*}} and
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; CHECK: Detected a reduction operation: {{.*}} and
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; CHECK: Detected a reduction operation: {{.*}} and
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; CHECK: Detected a reduction operation: {{.*}} and
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; CHECK: Detected a reduction operation: {{.*}} and
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; CHECK: Detected a reduction operation: {{.*}} and
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entry:
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br label %vector.body
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vector.body:
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%lsr.iv = phi i64 [ %lsr.iv.next, %vector.body ], [ -4096, %entry ]
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%vec.phi = phi <4 x i32> [ <i32 -1, i32 -1, i32 -1, i32 -1>, %entry ], [ %6, %vector.body ]
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%vec.phi9 = phi <4 x i32> [ <i32 -1, i32 -1, i32 -1, i32 -1>, %entry ], [ %7, %vector.body ]
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%uglygep33 = getelementptr i8, i8* bitcast ([1024 x i32]* @a to i8*), i64 %lsr.iv
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%uglygep3334 = bitcast i8* %uglygep33 to <4 x i32>*
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%scevgep35 = getelementptr <4 x i32>, <4 x i32>* %uglygep3334, i64 256
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%wide.load = load <4 x i32>, <4 x i32>* %scevgep35, align 16
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%scevgep36 = getelementptr <4 x i32>, <4 x i32>* %uglygep3334, i64 257
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%wide.load10 = load <4 x i32>, <4 x i32>* %scevgep36, align 16
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%0 = and <4 x i32> %wide.load, %vec.phi
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%1 = and <4 x i32> %wide.load10, %vec.phi9
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%uglygep30 = getelementptr i8, i8* bitcast ([1024 x i32]* @a to i8*), i64 %lsr.iv
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%uglygep3031 = bitcast i8* %uglygep30 to <4 x i32>*
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%scevgep32 = getelementptr <4 x i32>, <4 x i32>* %uglygep3031, i64 258
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%wide.load.1 = load <4 x i32>, <4 x i32>* %scevgep32, align 16
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%uglygep27 = getelementptr i8, i8* bitcast ([1024 x i32]* @a to i8*), i64 %lsr.iv
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%uglygep2728 = bitcast i8* %uglygep27 to <4 x i32>*
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%scevgep29 = getelementptr <4 x i32>, <4 x i32>* %uglygep2728, i64 259
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%wide.load10.1 = load <4 x i32>, <4 x i32>* %scevgep29, align 16
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%2 = and <4 x i32> %wide.load.1, %0
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%3 = and <4 x i32> %wide.load10.1, %1
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%uglygep24 = getelementptr i8, i8* bitcast ([1024 x i32]* @a to i8*), i64 %lsr.iv
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%uglygep2425 = bitcast i8* %uglygep24 to <4 x i32>*
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%scevgep26 = getelementptr <4 x i32>, <4 x i32>* %uglygep2425, i64 260
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%wide.load.2 = load <4 x i32>, <4 x i32>* %scevgep26, align 16
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%uglygep21 = getelementptr i8, i8* bitcast ([1024 x i32]* @a to i8*), i64 %lsr.iv
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%uglygep2122 = bitcast i8* %uglygep21 to <4 x i32>*
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%scevgep23 = getelementptr <4 x i32>, <4 x i32>* %uglygep2122, i64 261
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%wide.load10.2 = load <4 x i32>, <4 x i32>* %scevgep23, align 16
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%4 = and <4 x i32> %wide.load.2, %2
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%5 = and <4 x i32> %wide.load10.2, %3
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%uglygep18 = getelementptr i8, i8* bitcast ([1024 x i32]* @a to i8*), i64 %lsr.iv
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%uglygep1819 = bitcast i8* %uglygep18 to <4 x i32>*
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%scevgep20 = getelementptr <4 x i32>, <4 x i32>* %uglygep1819, i64 262
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%wide.load.3 = load <4 x i32>, <4 x i32>* %scevgep20, align 16
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%uglygep = getelementptr i8, i8* bitcast ([1024 x i32]* @a to i8*), i64 %lsr.iv
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%uglygep17 = bitcast i8* %uglygep to <4 x i32>*
|
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%scevgep = getelementptr <4 x i32>, <4 x i32>* %uglygep17, i64 263
|
||||
%wide.load10.3 = load <4 x i32>, <4 x i32>* %scevgep, align 16
|
||||
%6 = and <4 x i32> %wide.load.3, %4
|
||||
%7 = and <4 x i32> %wide.load10.3, %5
|
||||
%lsr.iv.next = add nsw i64 %lsr.iv, 128
|
||||
%8 = icmp eq i64 %lsr.iv.next, 0
|
||||
br i1 %8, label %middle.block, label %vector.body
|
||||
|
||||
middle.block:
|
||||
%bin.rdx = and <4 x i32> %7, %6
|
||||
%rdx.shuf = shufflevector <4 x i32> %bin.rdx, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
|
||||
%bin.rdx11 = and <4 x i32> %bin.rdx, %rdx.shuf
|
||||
%rdx.shuf12 = shufflevector <4 x i32> %bin.rdx11, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
|
||||
%bin.rdx13 = and <4 x i32> %bin.rdx11, %rdx.shuf12
|
||||
%9 = extractelement <4 x i32> %bin.rdx13, i32 0
|
||||
ret i32 %9
|
||||
}
|
||||
|
||||
define float @reduce_add_float(float* nocapture readonly %a) {
|
||||
; CHECK-LABEL: reduce_add_float
|
||||
; CHECK: Detected a reduction operation: {{.*}} fadd fast
|
||||
; CHECK: Detected a reduction operation: {{.*}} fadd fast
|
||||
; CHECK: Detected a reduction operation: {{.*}} fadd fast
|
||||
; CHECK: Detected a reduction operation: {{.*}} fadd fast
|
||||
; CHECK: Detected a reduction operation: {{.*}} fadd fast
|
||||
; CHECK: Detected a reduction operation: {{.*}} fadd fast
|
||||
; CHECK: Detected a reduction operation: {{.*}} fadd fast
|
||||
; CHECK: Detected a reduction operation: {{.*}} fadd fast
|
||||
; CHECK: Detected a reduction operation: {{.*}} fadd fast
|
||||
; CHECK: Detected a reduction operation: {{.*}} fadd fast
|
||||
; CHECK: Detected a reduction operation: {{.*}} fadd fast
|
||||
;
|
||||
entry:
|
||||
br label %vector.body
|
||||
|
||||
vector.body:
|
||||
%index = phi i64 [ 0, %entry ], [ %index.next.4, %vector.body ]
|
||||
%vec.phi = phi <4 x float> [ zeroinitializer, %entry ], [ %28, %vector.body ]
|
||||
%vec.phi9 = phi <4 x float> [ zeroinitializer, %entry ], [ %29, %vector.body ]
|
||||
%0 = getelementptr inbounds float, float* %a, i64 %index
|
||||
%1 = bitcast float* %0 to <4 x float>*
|
||||
%wide.load = load <4 x float>, <4 x float>* %1, align 4
|
||||
%2 = getelementptr float, float* %0, i64 4
|
||||
%3 = bitcast float* %2 to <4 x float>*
|
||||
%wide.load10 = load <4 x float>, <4 x float>* %3, align 4
|
||||
%4 = fadd fast <4 x float> %wide.load, %vec.phi
|
||||
%5 = fadd fast <4 x float> %wide.load10, %vec.phi9
|
||||
%index.next = add nuw nsw i64 %index, 8
|
||||
%6 = getelementptr inbounds float, float* %a, i64 %index.next
|
||||
%7 = bitcast float* %6 to <4 x float>*
|
||||
%wide.load.1 = load <4 x float>, <4 x float>* %7, align 4
|
||||
%8 = getelementptr float, float* %6, i64 4
|
||||
%9 = bitcast float* %8 to <4 x float>*
|
||||
%wide.load10.1 = load <4 x float>, <4 x float>* %9, align 4
|
||||
%10 = fadd fast <4 x float> %wide.load.1, %4
|
||||
%11 = fadd fast <4 x float> %wide.load10.1, %5
|
||||
%index.next.1 = add nsw i64 %index, 16
|
||||
%12 = getelementptr inbounds float, float* %a, i64 %index.next.1
|
||||
%13 = bitcast float* %12 to <4 x float>*
|
||||
%wide.load.2 = load <4 x float>, <4 x float>* %13, align 4
|
||||
%14 = getelementptr float, float* %12, i64 4
|
||||
%15 = bitcast float* %14 to <4 x float>*
|
||||
%wide.load10.2 = load <4 x float>, <4 x float>* %15, align 4
|
||||
%16 = fadd fast <4 x float> %wide.load.2, %10
|
||||
%17 = fadd fast <4 x float> %wide.load10.2, %11
|
||||
%index.next.2 = add nsw i64 %index, 24
|
||||
%18 = getelementptr inbounds float, float* %a, i64 %index.next.2
|
||||
%19 = bitcast float* %18 to <4 x float>*
|
||||
%wide.load.3 = load <4 x float>, <4 x float>* %19, align 4
|
||||
%20 = getelementptr float, float* %18, i64 4
|
||||
%21 = bitcast float* %20 to <4 x float>*
|
||||
%wide.load10.3 = load <4 x float>, <4 x float>* %21, align 4
|
||||
%22 = fadd fast <4 x float> %wide.load.3, %16
|
||||
%23 = fadd fast <4 x float> %wide.load10.3, %17
|
||||
%index.next.3 = add nsw i64 %index, 32
|
||||
%24 = getelementptr inbounds float, float* %a, i64 %index.next.3
|
||||
%25 = bitcast float* %24 to <4 x float>*
|
||||
%wide.load.4 = load <4 x float>, <4 x float>* %25, align 4
|
||||
%26 = getelementptr float, float* %24, i64 4
|
||||
%27 = bitcast float* %26 to <4 x float>*
|
||||
%wide.load10.4 = load <4 x float>, <4 x float>* %27, align 4
|
||||
%28 = fadd fast <4 x float> %wide.load.4, %22
|
||||
%29 = fadd fast <4 x float> %wide.load10.4, %23
|
||||
%index.next.4 = add nsw i64 %index, 40
|
||||
%30 = icmp eq i64 %index.next.4, 1000
|
||||
br i1 %30, label %middle.block, label %vector.body
|
||||
|
||||
middle.block:
|
||||
%.lcssa15 = phi <4 x float> [ %29, %vector.body ]
|
||||
%.lcssa = phi <4 x float> [ %28, %vector.body ]
|
||||
%bin.rdx = fadd fast <4 x float> %.lcssa15, %.lcssa
|
||||
%rdx.shuf = shufflevector <4 x float> %bin.rdx, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
|
||||
%bin.rdx11 = fadd fast <4 x float> %bin.rdx, %rdx.shuf
|
||||
%rdx.shuf12 = shufflevector <4 x float> %bin.rdx11, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
|
||||
%bin.rdx13 = fadd fast <4 x float> %bin.rdx11, %rdx.shuf12
|
||||
%31 = extractelement <4 x float> %bin.rdx13, i32 0
|
||||
ret float %31
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user