RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-06 03:08:43 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Fix that pesky floats in integer regs problem by assigning the f32 type to

Browse Source 
the correct register class.  Also remove the loading of float data into int
regs part of varargs; it will need to be implemented differently later.

llvm-svn: 20857
This commit is contained in:
Nate Begeman 2005-03-26 08:25:22 +00:00
parent 31d175d1e5
commit 6b0fbf811f
1 changed files with 4 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/PowerPC/PPC32ISelPattern.cpp
View File

@ -44,7 +44,7 @@ namespace {
// Set up the register classes.
addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
addRegisterClass(MVT::f32, PPC32::GPRCRegisterClass);
addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
computeRegisterProperties();
@ -322,13 +322,9 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
// store only the non-fixed arguments in a vararg function.
Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
Args[i].first, PtrOff));
if (GPR_remaining > 0)
args_to_use.push_back(DAG.getLoad(MVT::i32, Chain, PtrOff));
if (GPR_remaining > 1) {
SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
args_to_use.push_back(DAG.getLoad(MVT::i32, Chain, PtrOff));
}
// FIXME: Need a way to communicate to the ISD::CALL select code
// that a particular argument is non-fixed so that we can load them
// into the correct GPR to shadow the FPR
}
args_to_use.push_back(Args[i].first);
--FPR_remaining;