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Add definition of a base class for logical shift/rotate instructions with two

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source registers and redefine 32-bit and 64-bit instructions.

llvm-svn: 142210
This commit is contained in:
Akira Hatanaka 2011-10-17 18:17:58 +00:00
parent df4af2dd0b
commit 6b17ee5b50
2 changed files with 12 additions and 20 deletions
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16
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -51,14 +51,6 @@ class shift_rotate_imm64_32<bits<6> func, bits<5> isRotate, string instr_asm,
shift_rotate_imm<func, isRotate, instr_asm, OpNode, imm32_63, shamt_64,
CPU64Regs>;
class LogicR_shift_rotate_reg64<bits<6> func, bits<5> _shamt, string instr_asm,
SDNode OpNode>:
FR<0x00, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$c, CPU64Regs:$b),
!strconcat(instr_asm, "\t$dst, $b, $c"),
[(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], IIAlu> {
let shamt = _shamt;
}
// Mul, Div
let Defs = [HI64, LO64] in {
let isCommutable = 1 in
@ -124,15 +116,15 @@ def DSRA : shift_rotate_imm64<0x3b, 0x00, "dsra", sra>;
def DSLL32 : shift_rotate_imm64_32<0x3c, 0x00, "dsll32", shl>;
def DSRL32 : shift_rotate_imm64_32<0x3e, 0x00, "dsrl32", srl>;
def DSRA32 : shift_rotate_imm64_32<0x3f, 0x00, "dsra32", sra>;
def DSLLV : LogicR_shift_rotate_reg64<0x24, 0x00, "dsllv", shl>;
def DSRLV : LogicR_shift_rotate_reg64<0x26, 0x00, "dsrlv", srl>;
def DSRAV : LogicR_shift_rotate_reg64<0x27, 0x00, "dsrav", sra>;
def DSLLV : shift_rotate_reg<0x24, 0x00, "dsllv", shl, CPU64Regs>;
def DSRLV : shift_rotate_reg<0x26, 0x00, "dsrlv", srl, CPU64Regs>;
def DSRAV : shift_rotate_reg<0x27, 0x00, "dsrav", sra, CPU64Regs>;
// Rotate Instructions
let Predicates = [HasMips64r2] in {
def DROTR : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>;
def DROTR32 : shift_rotate_imm64_32<0x3e, 0x01, "drotr32", rotr>;
def DROTRV : LogicR_shift_rotate_reg64<0x16, 0x01, "drotrv", rotr>;
def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>;
}
/// Load and Store Instructions

16
lib/Target/Mips/MipsInstrInfo.td
View File

@ -313,11 +313,11 @@ class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm,
SDNode OpNode>:
shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>;
class LogicR_shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
SDNode OpNode>:
FR<0x00, func, (outs CPURegs:$rd), (ins CPURegs:$rs, CPURegs:$rt),
class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
SDNode OpNode, RegisterClass RC>:
FR<0x00, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
!strconcat(instr_asm, "\t$rd, $rt, $rs"),
[(set CPURegs:$rd, (OpNode CPURegs:$rt, CPURegs:$rs))], IIAlu> {
[(set RC:$rd, (OpNode RC:$rt, RC:$rs))], IIAlu> {
let shamt = isRotate;
}
@ -659,14 +659,14 @@ def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>;
def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>;
def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>;
def SLLV : LogicR_shift_rotate_reg<0x04, 0x00, "sllv", shl>;
def SRLV : LogicR_shift_rotate_reg<0x06, 0x00, "srlv", srl>;
def SRAV : LogicR_shift_rotate_reg<0x07, 0x00, "srav", sra>;
def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>;
def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>;
def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>;
// Rotate Instructions
let Predicates = [HasMips32r2] in {
def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>;
def ROTRV : LogicR_shift_rotate_reg<0x06, 0x01, "rotrv", rotr>;
def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>;
}
/// Load and Store Instructions