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Add ARMv6 itineraries.
llvm-svn: 89218
This commit is contained in:
David Goodwin
parent
6993e5d049
commit
6b56e77397
@ -89,16 +89,18 @@ def : ProcNoItin<"xscale", [ArchV5TE]>;
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def : ProcNoItin<"iwmmxt", [ArchV5TE]>;
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// V6 Processors.
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def : ProcNoItin<"arm1136j-s", [ArchV6]>;
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def : ProcNoItin<"arm1136jf-s", [ArchV6, FeatureVFP2]>;
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def : ProcNoItin<"arm1176jz-s", [ArchV6]>;
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def : ProcNoItin<"arm1176jzf-s", [ArchV6, FeatureVFP2]>;
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def : ProcNoItin<"mpcorenovfp", [ArchV6]>;
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def : ProcNoItin<"mpcore", [ArchV6, FeatureVFP2]>;
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def : Processor<"arm1136j-s", ARMV6Itineraries, [ArchV6]>;
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def : Processor<"arm1136jf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
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def : Processor<"arm1176jz-s", ARMV6Itineraries, [ArchV6]>;
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def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
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def : Processor<"mpcorenovfp", ARMV6Itineraries, [ArchV6]>;
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def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
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// V6T2 Processors.
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def : ProcNoItin<"arm1156t2-s", [ArchV6T2, FeatureThumb2]>;
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def : ProcNoItin<"arm1156t2f-s", [ArchV6T2, FeatureThumb2, FeatureVFP2]>;
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def : Processor<"arm1156t2-s", ARMV6Itineraries,
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[ArchV6T2, FeatureThumb2]>;
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def : Processor<"arm1156t2f-s", ARMV6Itineraries,
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[ArchV6T2, FeatureThumb2, FeatureVFP2]>;
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// V7 Processors.
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def : Processor<"cortex-a8", CortexA8Itineraries,
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@ -11,4 +11,190 @@
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//
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//===----------------------------------------------------------------------===//
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// TODO: Add model for an ARM11
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// Model based on ARM1176
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//
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// Scheduling information derived from "ARM1176JZF-S Technical Reference Manual".
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//
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def ARMV6Itineraries : ProcessorItineraries<[
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//
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// No operand cycles
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InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0]>]>,
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//
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// Binary Instructions that produce a result
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InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0]>], [2, 2]>,
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InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0]>], [2, 2, 2]>,
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InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0]>], [2, 2, 1]>,
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InstrItinData<IIC_iALUsr , [InstrStage<2, [FU_Pipe0]>], [3, 3, 2, 1]>,
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//
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// Unary Instructions that produce a result
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InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0]>], [2, 2]>,
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InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0]>], [2, 1]>,
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InstrItinData<IIC_iUNAsr , [InstrStage<2, [FU_Pipe0]>], [3, 2, 1]>,
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//
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// Compare instructions
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InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0]>], [2]>,
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InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0]>], [2, 2]>,
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InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0]>], [2, 1]>,
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InstrItinData<IIC_iCMPsr , [InstrStage<2, [FU_Pipe0]>], [3, 2, 1]>,
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//
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// Move instructions, unconditional
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InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0]>], [2]>,
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InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0]>], [2, 2]>,
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InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0]>], [2, 1]>,
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InstrItinData<IIC_iMOVsr , [InstrStage<2, [FU_Pipe0]>], [3, 2, 1]>,
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//
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// Move instructions, conditional
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InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0]>], [3]>,
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InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0]>], [3, 2]>,
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InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>], [3, 1]>,
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InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>], [4, 2, 1]>,
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// Integer multiply pipeline
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//
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InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>], [4, 1, 1]>,
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InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe0]>], [4, 1, 1, 2]>,
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InstrItinData<IIC_iMUL32 , [InstrStage<2, [FU_Pipe0]>], [5, 1, 1]>,
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InstrItinData<IIC_iMAC32 , [InstrStage<2, [FU_Pipe0]>], [5, 1, 1, 2]>,
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InstrItinData<IIC_iMUL64 , [InstrStage<3, [FU_Pipe0]>], [6, 1, 1]>,
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InstrItinData<IIC_iMAC64 , [InstrStage<3, [FU_Pipe0]>], [6, 1, 1, 2]>,
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// Integer load pipeline
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//
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// Immediate offset
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InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Pipe0]>], [4, 1]>,
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//
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// Register offset
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InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Pipe0]>], [4, 1, 1]>,
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//
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// Scaled register offset, issues over 2 cycles
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InstrItinData<IIC_iLoadsi , [InstrStage<2, [FU_Pipe0]>], [5, 2, 1]>,
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//
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// Immediate offset with update
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InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>], [4, 2, 1]>,
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//
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// Register offset with update
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InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>], [4, 2, 1, 1]>,
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//
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// Scaled register offset with update, issues over 2 cycles
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InstrItinData<IIC_iLoadsiu , [InstrStage<2, [FU_Pipe0]>], [5, 2, 2, 1]>,
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//
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// Load multiple
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InstrItinData<IIC_iLoadm , [InstrStage<3, [FU_Pipe0]>]>,
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// Integer store pipeline
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//
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// Immediate offset
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InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Pipe0]>], [2, 1]>,
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//
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// Register offset
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InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Pipe0]>], [2, 1, 1]>,
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//
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// Scaled register offset, issues over 2 cycles
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InstrItinData<IIC_iStoresi , [InstrStage<2, [FU_Pipe0]>], [2, 2, 1]>,
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//
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// Immediate offset with update
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InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>], [2, 2, 1]>,
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//
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// Register offset with update
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InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>], [2, 2, 1, 1]>,
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//
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// Scaled register offset with update, issues over 2 cycles
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InstrItinData<IIC_iStoresiu, [InstrStage<2, [FU_Pipe0]>], [2, 2, 2, 1]>,
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//
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// Store multiple
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InstrItinData<IIC_iStorem , [InstrStage<3, [FU_Pipe0]>]>,
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// Branch
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//
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// no delay slots, so the latency of a branch is unimportant
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InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
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// VFP
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// Issue through integer pipeline, and execute in NEON unit. We assume
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// RunFast mode so that NFP pipeline is used for single-precision when
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// possible.
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//
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// FP Special Register to Integer Register File Move
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InstrItinData<IIC_fpSTAT , [InstrStage<1, [FU_Pipe0]>], [3]>,
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//
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// Single-precision FP Unary
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InstrItinData<IIC_fpUNA32 , [InstrStage<1, [FU_Pipe0]>], [5, 2]>,
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//
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// Double-precision FP Unary
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InstrItinData<IIC_fpUNA64 , [InstrStage<1, [FU_Pipe0]>], [5, 2]>,
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//
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// Single-precision FP Compare
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InstrItinData<IIC_fpCMP32 , [InstrStage<1, [FU_Pipe0]>], [2, 2]>,
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//
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// Double-precision FP Compare
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InstrItinData<IIC_fpCMP64 , [InstrStage<1, [FU_Pipe0]>], [2, 2]>,
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//
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// Single to Double FP Convert
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InstrItinData<IIC_fpCVTSD , [InstrStage<1, [FU_Pipe0]>], [5, 2]>,
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//
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// Double to Single FP Convert
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InstrItinData<IIC_fpCVTDS , [InstrStage<1, [FU_Pipe0]>], [5, 2]>,
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//
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// Single-Precision FP to Integer Convert
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InstrItinData<IIC_fpCVTSI , [InstrStage<1, [FU_Pipe0]>], [9, 2]>,
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//
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// Double-Precision FP to Integer Convert
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InstrItinData<IIC_fpCVTDI , [InstrStage<1, [FU_Pipe0]>], [9, 2]>,
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//
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// Integer to Single-Precision FP Convert
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InstrItinData<IIC_fpCVTIS , [InstrStage<1, [FU_Pipe0]>], [9, 2]>,
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//
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// Integer to Double-Precision FP Convert
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InstrItinData<IIC_fpCVTID , [InstrStage<1, [FU_Pipe0]>], [9, 2]>,
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//
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// Single-precision FP ALU
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InstrItinData<IIC_fpALU32 , [InstrStage<1, [FU_Pipe0]>], [9, 2, 2]>,
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//
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// Double-precision FP ALU
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InstrItinData<IIC_fpALU64 , [InstrStage<1, [FU_Pipe0]>], [9, 2, 2]>,
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//
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// Single-precision FP Multiply
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InstrItinData<IIC_fpMUL32 , [InstrStage<1, [FU_Pipe0]>], [9, 2, 2]>,
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//
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// Double-precision FP Multiply
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InstrItinData<IIC_fpMUL64 , [InstrStage<2, [FU_Pipe0]>], [9, 2, 2]>,
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//
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// Single-precision FP MAC
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InstrItinData<IIC_fpMAC32 , [InstrStage<1, [FU_Pipe0]>], [9, 2, 2, 2]>,
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//
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// Double-precision FP MAC
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InstrItinData<IIC_fpMAC64 , [InstrStage<2, [FU_Pipe0]>], [9, 2, 2, 2]>,
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//
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// Single-precision FP DIV
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InstrItinData<IIC_fpDIV32 , [InstrStage<15, [FU_Pipe0]>], [20, 2, 2]>,
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//
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// Double-precision FP DIV
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InstrItinData<IIC_fpDIV64 , [InstrStage<29, [FU_Pipe0]>], [34, 2, 2]>,
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//
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// Single-precision FP SQRT
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InstrItinData<IIC_fpSQRT32 , [InstrStage<15, [FU_Pipe0]>], [20, 2, 2]>,
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//
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// Double-precision FP SQRT
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InstrItinData<IIC_fpSQRT64 , [InstrStage<29, [FU_Pipe0]>], [34, 2, 2]>,
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//
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// Single-precision FP Load
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InstrItinData<IIC_fpLoad32 , [InstrStage<1, [FU_Pipe0]>], [5, 2, 2]>,
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//
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// Double-precision FP Load
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InstrItinData<IIC_fpLoad64 , [InstrStage<1, [FU_Pipe0]>], [5, 2, 2]>,
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//
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// FP Load Multiple
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InstrItinData<IIC_fpLoadm , [InstrStage<3, [FU_Pipe0]>]>,
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//
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// Single-precision FP Store
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InstrItinData<IIC_fpStore32 , [InstrStage<1, [FU_Pipe0]>], [2, 2, 2]>,
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//
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// Double-precision FP Store
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// use FU_Issue to enforce the 1 load/store per cycle limit
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InstrItinData<IIC_fpStore64 , [InstrStage<1, [FU_Pipe0]>], [2, 2, 2]>,
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//
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// FP Store Multiple
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InstrItinData<IIC_fpStorem , [InstrStage<3, [FU_Pipe0]>]>
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]>;
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@ -184,7 +184,7 @@ def CortexA8Itineraries : ProcessorItineraries<[
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//
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// Single-precision FP Compare
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InstrItinData<IIC_fpCMP32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [7, 1]>,
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InstrStage<1, [FU_NPipe]>], [1, 1]>,
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//
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// Double-precision FP Compare
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InstrItinData<IIC_fpCMP64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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@ -221,7 +221,7 @@ def CortexA8Itineraries : ProcessorItineraries<[
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//
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// Single-precision FP ALU
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InstrItinData<IIC_fpALU32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [7, 1]>,
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InstrStage<1, [FU_NPipe]>], [7, 1, 1]>,
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//
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// Double-precision FP ALU
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InstrItinData<IIC_fpALU64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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@ -230,7 +230,7 @@ def CortexA8Itineraries : ProcessorItineraries<[
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//
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// Single-precision FP Multiply
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InstrItinData<IIC_fpMUL32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [7, 1]>,
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InstrStage<1, [FU_NPipe]>], [7, 1, 1]>,
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//
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// Double-precision FP Multiply
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InstrItinData<IIC_fpMUL64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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@ -239,7 +239,7 @@ def CortexA8Itineraries : ProcessorItineraries<[
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//
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// Single-precision FP MAC
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InstrItinData<IIC_fpMAC32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [7, 1]>,
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InstrStage<1, [FU_NPipe]>], [7, 2, 1, 1]>,
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//
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// Double-precision FP MAC
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InstrItinData<IIC_fpMAC64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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