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AMDGPU: Constant fold when immediate is materialized
In future commits these patterns will appear after moveToVALU changes. llvm-svn: 291615
This commit is contained in:
Matt Arsenault
parent
740f03ad29
commit
6b917afcf9
@ -25,25 +25,6 @@ using namespace llvm;
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namespace {
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class SIFoldOperands : public MachineFunctionPass {
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public:
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static char ID;
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public:
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SIFoldOperands() : MachineFunctionPass(ID) {
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initializeSIFoldOperandsPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return "SI Fold Operands"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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struct FoldCandidate {
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MachineInstr *UseMI;
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union {
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@ -79,6 +60,36 @@ struct FoldCandidate {
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}
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};
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class SIFoldOperands : public MachineFunctionPass {
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public:
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static char ID;
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MachineRegisterInfo *MRI;
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const SIInstrInfo *TII;
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const SIRegisterInfo *TRI;
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void foldOperand(MachineOperand &OpToFold,
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MachineInstr *UseMI,
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unsigned UseOpIdx,
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SmallVectorImpl<FoldCandidate> &FoldList,
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SmallVectorImpl<MachineInstr *> &CopiesToReplace) const;
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void foldInstOperand(MachineInstr &MI, MachineOperand &OpToFold) const;
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public:
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SIFoldOperands() : MachineFunctionPass(ID) {
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initializeSIFoldOperandsPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return "SI Fold Operands"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // End anonymous namespace.
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INITIALIZE_PASS(SIFoldOperands, DEBUG_TYPE,
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@ -141,7 +152,7 @@ static bool updateOperand(FoldCandidate &Fold,
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return false;
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}
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static bool isUseMIInFoldList(const std::vector<FoldCandidate> &FoldList,
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static bool isUseMIInFoldList(ArrayRef<FoldCandidate> FoldList,
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const MachineInstr *MI) {
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for (auto Candidate : FoldList) {
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if (Candidate.UseMI == MI)
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@ -150,7 +161,7 @@ static bool isUseMIInFoldList(const std::vector<FoldCandidate> &FoldList,
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return false;
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}
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static bool tryAddToFoldList(std::vector<FoldCandidate> &FoldList,
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static bool tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
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MachineInstr *MI, unsigned OpNo,
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MachineOperand *OpToFold,
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const SIInstrInfo *TII) {
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@ -227,12 +238,12 @@ static bool isUseSafeToFold(const MachineInstr &MI,
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//return !MI.hasRegisterImplicitUseOperand(UseMO.getReg());
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}
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static void foldOperand(MachineOperand &OpToFold, MachineInstr *UseMI,
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unsigned UseOpIdx,
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std::vector<FoldCandidate> &FoldList,
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SmallVectorImpl<MachineInstr *> &CopiesToReplace,
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const SIInstrInfo *TII, const SIRegisterInfo &TRI,
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MachineRegisterInfo &MRI) {
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void SIFoldOperands::foldOperand(
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MachineOperand &OpToFold,
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MachineInstr *UseMI,
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unsigned UseOpIdx,
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SmallVectorImpl<FoldCandidate> &FoldList,
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SmallVectorImpl<MachineInstr *> &CopiesToReplace) const {
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const MachineOperand &UseOp = UseMI->getOperand(UseOpIdx);
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if (!isUseSafeToFold(*UseMI, UseOp))
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@ -264,7 +275,7 @@ static void foldOperand(MachineOperand &OpToFold, MachineInstr *UseMI,
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unsigned RegSeqDstSubReg = UseMI->getOperand(UseOpIdx + 1).getImm();
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for (MachineRegisterInfo::use_iterator
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RSUse = MRI.use_begin(RegSeqDstReg), RSE = MRI.use_end();
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RSUse = MRI->use_begin(RegSeqDstReg), RSE = MRI->use_end();
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RSUse != RSE; ++RSUse) {
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MachineInstr *RSUseMI = RSUse->getParent();
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@ -272,7 +283,7 @@ static void foldOperand(MachineOperand &OpToFold, MachineInstr *UseMI,
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continue;
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foldOperand(OpToFold, RSUseMI, RSUse.getOperandNo(), FoldList,
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CopiesToReplace, TII, TRI, MRI);
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CopiesToReplace);
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}
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return;
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@ -287,8 +298,8 @@ static void foldOperand(MachineOperand &OpToFold, MachineInstr *UseMI,
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unsigned DestReg = UseMI->getOperand(0).getReg();
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const TargetRegisterClass *DestRC
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= TargetRegisterInfo::isVirtualRegister(DestReg) ?
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MRI.getRegClass(DestReg) :
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TRI.getPhysRegClass(DestReg);
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MRI->getRegClass(DestReg) :
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TRI->getPhysRegClass(DestReg);
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unsigned MovOp = TII->getMovOpcode(DestRC);
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if (MovOp == AMDGPU::COPY)
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@ -318,7 +329,7 @@ static void foldOperand(MachineOperand &OpToFold, MachineInstr *UseMI,
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const MCInstrDesc &FoldDesc = OpToFold.getParent()->getDesc();
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const TargetRegisterClass *FoldRC =
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TRI.getRegClass(FoldDesc.OpInfo[0].RegClass);
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TRI->getRegClass(FoldDesc.OpInfo[0].RegClass);
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APInt Imm(TII->operandBitWidth(FoldDesc.OpInfo[1].OperandType),
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OpToFold.getImm());
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@ -328,8 +339,8 @@ static void foldOperand(MachineOperand &OpToFold, MachineInstr *UseMI,
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unsigned UseReg = UseOp.getReg();
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const TargetRegisterClass *UseRC
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= TargetRegisterInfo::isVirtualRegister(UseReg) ?
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MRI.getRegClass(UseReg) :
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TRI.getPhysRegClass(UseReg);
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MRI->getRegClass(UseReg) :
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TRI->getPhysRegClass(UseReg);
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assert(Imm.getBitWidth() == 64);
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@ -349,20 +360,51 @@ static void foldOperand(MachineOperand &OpToFold, MachineInstr *UseMI,
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}
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static bool evalBinaryInstruction(unsigned Opcode, int32_t &Result,
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int32_t LHS, int32_t RHS) {
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uint32_t LHS, uint32_t RHS) {
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switch (Opcode) {
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case AMDGPU::V_AND_B32_e64:
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case AMDGPU::V_AND_B32_e32:
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case AMDGPU::S_AND_B32:
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Result = LHS & RHS;
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return true;
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case AMDGPU::V_OR_B32_e64:
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case AMDGPU::V_OR_B32_e32:
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case AMDGPU::S_OR_B32:
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Result = LHS | RHS;
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return true;
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case AMDGPU::V_XOR_B32_e64:
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case AMDGPU::V_XOR_B32_e32:
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case AMDGPU::S_XOR_B32:
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Result = LHS ^ RHS;
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return true;
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case AMDGPU::V_LSHL_B32_e64:
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case AMDGPU::V_LSHL_B32_e32:
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case AMDGPU::S_LSHL_B32:
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// The instruction ignores the high bits for out of bounds shifts.
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Result = LHS << (RHS & 31);
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return true;
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case AMDGPU::V_LSHLREV_B32_e64:
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case AMDGPU::V_LSHLREV_B32_e32:
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Result = RHS << (LHS & 31);
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return true;
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case AMDGPU::V_LSHR_B32_e64:
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case AMDGPU::V_LSHR_B32_e32:
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case AMDGPU::S_LSHR_B32:
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Result = LHS >> (RHS & 31);
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return true;
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case AMDGPU::V_LSHRREV_B32_e64:
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case AMDGPU::V_LSHRREV_B32_e32:
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Result = RHS >> (LHS & 31);
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return true;
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case AMDGPU::V_ASHR_I32_e64:
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case AMDGPU::V_ASHR_I32_e32:
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case AMDGPU::S_ASHR_I32:
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Result = static_cast<int32_t>(LHS) >> (RHS & 31);
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return true;
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case AMDGPU::V_ASHRREV_I32_e64:
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case AMDGPU::V_ASHRREV_I32_e32:
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Result = static_cast<int32_t>(RHS) >> (LHS & 31);
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return true;
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default:
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return false;
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}
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@ -390,33 +432,47 @@ static void mutateCopyOp(MachineInstr &MI, const MCInstrDesc &NewDesc) {
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stripExtraCopyOperands(MI);
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}
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// Try to simplify operations with a constant that may appear after instruction
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// selection.
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static bool tryConstantFoldOp(MachineRegisterInfo &MRI,
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const SIInstrInfo *TII,
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MachineInstr *MI) {
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unsigned Opc = MI->getOpcode();
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static MachineOperand *getImmOrMaterializedImm(MachineRegisterInfo &MRI,
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MachineOperand &Op) {
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if (Op.isReg()) {
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// If this has a subregister, it obviously is a register source.
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if (Op.getSubReg() != AMDGPU::NoSubRegister)
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return &Op;
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if (Opc == AMDGPU::V_NOT_B32_e64 || Opc == AMDGPU::V_NOT_B32_e32 ||
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Opc == AMDGPU::S_NOT_B32) {
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MachineOperand &Src0 = MI->getOperand(1);
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if (Src0.isImm()) {
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Src0.setImm(~Src0.getImm());
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mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_NOT_B32)));
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return true;
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MachineInstr *Def = MRI.getVRegDef(Op.getReg());
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if (Def->isMoveImmediate()) {
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MachineOperand &ImmSrc = Def->getOperand(1);
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if (ImmSrc.isImm())
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return &ImmSrc;
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}
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return false;
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}
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if (!MI->isCommutable())
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return &Op;
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}
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// Try to simplify operations with a constant that may appear after instruction
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// selection.
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// TODO: See if a frame index with a fixed offset can fold.
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static bool tryConstantFoldOp(MachineRegisterInfo &MRI,
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const SIInstrInfo *TII,
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MachineInstr *MI,
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MachineOperand *ImmOp) {
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unsigned Opc = MI->getOpcode();
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if (Opc == AMDGPU::V_NOT_B32_e64 || Opc == AMDGPU::V_NOT_B32_e32 ||
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Opc == AMDGPU::S_NOT_B32) {
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MI->getOperand(1).ChangeToImmediate(~ImmOp->getImm());
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mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_NOT_B32)));
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return true;
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}
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int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
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if (Src1Idx == -1)
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return false;
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int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
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int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
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MachineOperand *Src0 = getImmOrMaterializedImm(MRI, MI->getOperand(Src0Idx));
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MachineOperand *Src1 = getImmOrMaterializedImm(MRI, MI->getOperand(Src1Idx));
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MachineOperand *Src0 = &MI->getOperand(Src0Idx);
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MachineOperand *Src1 = &MI->getOperand(Src1Idx);
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if (!Src0->isImm() && !Src1->isImm())
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return false;
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@ -431,19 +487,26 @@ static bool tryConstantFoldOp(MachineRegisterInfo &MRI,
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const SIRegisterInfo &TRI = TII->getRegisterInfo();
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bool IsSGPR = TRI.isSGPRReg(MRI, MI->getOperand(0).getReg());
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Src0->setImm(NewImm);
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// Be careful to change the right operand, src0 may belong to a different
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// instruction.
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MI->getOperand(Src0Idx).ChangeToImmediate(NewImm);
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MI->RemoveOperand(Src1Idx);
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mutateCopyOp(*MI, TII->get(getMovOpc(IsSGPR)));
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return true;
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}
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if (!MI->isCommutable())
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return false;
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if (Src0->isImm() && !Src1->isImm()) {
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std::swap(Src0, Src1);
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std::swap(Src0Idx, Src1Idx);
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}
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int32_t Src1Val = static_cast<int32_t>(Src1->getImm());
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if (Opc == AMDGPU::V_OR_B32_e64 || Opc == AMDGPU::S_OR_B32) {
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if (Opc == AMDGPU::V_OR_B32_e64 ||
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Opc == AMDGPU::V_OR_B32_e32 ||
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Opc == AMDGPU::S_OR_B32) {
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if (Src1Val == 0) {
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// y = or x, 0 => y = copy x
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MI->RemoveOperand(Src1Idx);
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@ -459,6 +522,7 @@ static bool tryConstantFoldOp(MachineRegisterInfo &MRI,
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}
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if (MI->getOpcode() == AMDGPU::V_AND_B32_e64 ||
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MI->getOpcode() == AMDGPU::V_AND_B32_e32 ||
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MI->getOpcode() == AMDGPU::S_AND_B32) {
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if (Src1Val == 0) {
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// y = and x, 0 => y = v_mov_b32 0
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@ -476,29 +540,136 @@ static bool tryConstantFoldOp(MachineRegisterInfo &MRI,
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}
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if (MI->getOpcode() == AMDGPU::V_XOR_B32_e64 ||
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MI->getOpcode() == AMDGPU::V_XOR_B32_e32 ||
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MI->getOpcode() == AMDGPU::S_XOR_B32) {
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if (Src1Val == 0) {
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// y = xor x, 0 => y = copy x
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MI->RemoveOperand(Src1Idx);
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mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
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return true;
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}
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}
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return false;
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}
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void SIFoldOperands::foldInstOperand(MachineInstr &MI,
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MachineOperand &OpToFold) const {
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// We need mutate the operands of new mov instructions to add implicit
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// uses of EXEC, but adding them invalidates the use_iterator, so defer
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// this.
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SmallVector<MachineInstr *, 4> CopiesToReplace;
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SmallVector<FoldCandidate, 4> FoldList;
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MachineOperand &Dst = MI.getOperand(0);
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bool FoldingImm = OpToFold.isImm() || OpToFold.isFI();
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if (FoldingImm) {
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unsigned NumLiteralUses = 0;
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MachineOperand *NonInlineUse = nullptr;
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int NonInlineUseOpNo = -1;
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MachineRegisterInfo::use_iterator NextUse, NextInstUse;
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for (MachineRegisterInfo::use_iterator
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Use = MRI->use_begin(Dst.getReg()), E = MRI->use_end();
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Use != E; Use = NextUse) {
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NextUse = std::next(Use);
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MachineInstr *UseMI = Use->getParent();
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unsigned OpNo = Use.getOperandNo();
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// Folding the immediate may reveal operations that can be constant
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// folded or replaced with a copy. This can happen for example after
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// frame indices are lowered to constants or from splitting 64-bit
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// constants.
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//
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// We may also encounter cases where one or both operands are
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// immediates materialized into a register, which would ordinarily not
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// be folded due to multiple uses or operand constraints.
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if (OpToFold.isImm() && tryConstantFoldOp(*MRI, TII, UseMI, &OpToFold)) {
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DEBUG(dbgs() << "Constant folded " << *UseMI <<'\n');
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// Some constant folding cases change the same immediate's use to a new
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// instruction, e.g. and x, 0 -> 0. Make sure we re-visit the user
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// again. The same constant folded instruction could also have a second
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// use operand.
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NextUse = MRI->use_begin(Dst.getReg());
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continue;
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}
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// Try to fold any inline immediate uses, and then only fold other
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// constants if they have one use.
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//
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// The legality of the inline immediate must be checked based on the use
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// operand, not the defining instruction, because 32-bit instructions
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// with 32-bit inline immediate sources may be used to materialize
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// constants used in 16-bit operands.
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//
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// e.g. it is unsafe to fold:
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// s_mov_b32 s0, 1.0 // materializes 0x3f800000
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// v_add_f16 v0, v1, s0 // 1.0 f16 inline immediate sees 0x00003c00
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// Folding immediates with more than one use will increase program size.
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// FIXME: This will also reduce register usage, which may be better
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// in some cases. A better heuristic is needed.
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if (TII->isInlineConstant(*UseMI, OpNo, OpToFold)) {
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foldOperand(OpToFold, UseMI, OpNo, FoldList, CopiesToReplace);
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} else {
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if (++NumLiteralUses == 1) {
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NonInlineUse = &*Use;
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NonInlineUseOpNo = OpNo;
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}
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}
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}
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if (NumLiteralUses == 1) {
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MachineInstr *UseMI = NonInlineUse->getParent();
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foldOperand(OpToFold, UseMI, NonInlineUseOpNo, FoldList, CopiesToReplace);
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}
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} else {
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// Folding register.
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for (MachineRegisterInfo::use_iterator
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Use = MRI->use_begin(Dst.getReg()), E = MRI->use_end();
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Use != E; ++Use) {
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MachineInstr *UseMI = Use->getParent();
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foldOperand(OpToFold, UseMI, Use.getOperandNo(),
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FoldList, CopiesToReplace);
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}
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}
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MachineFunction *MF = MI.getParent()->getParent();
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// Make sure we add EXEC uses to any new v_mov instructions created.
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for (MachineInstr *Copy : CopiesToReplace)
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Copy->addImplicitDefUseOperands(*MF);
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for (FoldCandidate &Fold : FoldList) {
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if (updateOperand(Fold, *TRI)) {
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// Clear kill flags.
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if (Fold.isReg()) {
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assert(Fold.OpToFold && Fold.OpToFold->isReg());
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// FIXME: Probably shouldn't bother trying to fold if not an
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// SGPR. PeepholeOptimizer can eliminate redundant VGPR->VGPR
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// copies.
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MRI->clearKillFlags(Fold.OpToFold->getReg());
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}
|
||||
DEBUG(dbgs() << "Folded source from " << MI << " into OpNo " <<
|
||||
static_cast<int>(Fold.UseOpNo) << " of " << *Fold.UseMI << '\n');
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
|
||||
if (skipFunction(*MF.getFunction()))
|
||||
return false;
|
||||
|
||||
const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
|
||||
|
||||
MachineRegisterInfo &MRI = MF.getRegInfo();
|
||||
const SIInstrInfo *TII = ST.getInstrInfo();
|
||||
const SIRegisterInfo &TRI = TII->getRegisterInfo();
|
||||
MRI = &MF.getRegInfo();
|
||||
TII = ST.getInstrInfo();
|
||||
TRI = &TII->getRegisterInfo();
|
||||
|
||||
for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
|
||||
BI != BE; ++BI) {
|
||||
BI != BE; ++BI) {
|
||||
|
||||
MachineBasicBlock &MBB = *BI;
|
||||
MachineBasicBlock::iterator I, Next;
|
||||
@ -512,8 +683,7 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
|
||||
MachineOperand &OpToFold = MI.getOperand(1);
|
||||
bool FoldingImm = OpToFold.isImm() || OpToFold.isFI();
|
||||
|
||||
// FIXME: We could also be folding things like FrameIndexes and
|
||||
// TargetIndexes.
|
||||
// FIXME: We could also be folding things like TargetIndexes.
|
||||
if (!FoldingImm && !OpToFold.isReg())
|
||||
continue;
|
||||
|
||||
@ -532,90 +702,7 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
|
||||
!TargetRegisterInfo::isVirtualRegister(Dst.getReg()))
|
||||
continue;
|
||||
|
||||
// We need mutate the operands of new mov instructions to add implicit
|
||||
// uses of EXEC, but adding them invalidates the use_iterator, so defer
|
||||
// this.
|
||||
SmallVector<MachineInstr *, 4> CopiesToReplace;
|
||||
|
||||
std::vector<FoldCandidate> FoldList;
|
||||
if (FoldingImm) {
|
||||
unsigned NumLiteralUses = 0;
|
||||
MachineOperand *NonInlineUse = nullptr;
|
||||
int NonInlineUseOpNo = -1;
|
||||
|
||||
// Try to fold any inline immediate uses, and then only fold other
|
||||
// constants if they have one use.
|
||||
//
|
||||
// The legality of the inline immediate must be checked based on the use
|
||||
// operand, not the defining instruction, because 32-bit instructions
|
||||
// with 32-bit inline immediate sources may be used to materialize
|
||||
// constants used in 16-bit operands.
|
||||
//
|
||||
// e.g. it is unsafe to fold:
|
||||
// s_mov_b32 s0, 1.0 // materializes 0x3f800000
|
||||
// v_add_f16 v0, v1, s0 // 1.0 f16 inline immediate sees 0x00003c00
|
||||
|
||||
// Folding immediates with more than one use will increase program size.
|
||||
// FIXME: This will also reduce register usage, which may be better
|
||||
// in some cases. A better heuristic is needed.
|
||||
for (MachineRegisterInfo::use_iterator
|
||||
Use = MRI.use_begin(Dst.getReg()), E = MRI.use_end();
|
||||
Use != E; ++Use) {
|
||||
MachineInstr *UseMI = Use->getParent();
|
||||
unsigned OpNo = Use.getOperandNo();
|
||||
|
||||
if (TII->isInlineConstant(*UseMI, OpNo, OpToFold)) {
|
||||
foldOperand(OpToFold, UseMI, OpNo, FoldList,
|
||||
CopiesToReplace, TII, TRI, MRI);
|
||||
} else {
|
||||
if (++NumLiteralUses == 1) {
|
||||
NonInlineUse = &*Use;
|
||||
NonInlineUseOpNo = OpNo;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (NumLiteralUses == 1) {
|
||||
MachineInstr *UseMI = NonInlineUse->getParent();
|
||||
foldOperand(OpToFold, UseMI, NonInlineUseOpNo, FoldList,
|
||||
CopiesToReplace, TII, TRI, MRI);
|
||||
}
|
||||
} else {
|
||||
// Folding register.
|
||||
for (MachineRegisterInfo::use_iterator
|
||||
Use = MRI.use_begin(Dst.getReg()), E = MRI.use_end();
|
||||
Use != E; ++Use) {
|
||||
MachineInstr *UseMI = Use->getParent();
|
||||
|
||||
foldOperand(OpToFold, UseMI, Use.getOperandNo(), FoldList,
|
||||
CopiesToReplace, TII, TRI, MRI);
|
||||
}
|
||||
}
|
||||
|
||||
// Make sure we add EXEC uses to any new v_mov instructions created.
|
||||
for (MachineInstr *Copy : CopiesToReplace)
|
||||
Copy->addImplicitDefUseOperands(MF);
|
||||
|
||||
for (FoldCandidate &Fold : FoldList) {
|
||||
if (updateOperand(Fold, TRI)) {
|
||||
// Clear kill flags.
|
||||
if (Fold.isReg()) {
|
||||
assert(Fold.OpToFold && Fold.OpToFold->isReg());
|
||||
// FIXME: Probably shouldn't bother trying to fold if not an
|
||||
// SGPR. PeepholeOptimizer can eliminate redundant VGPR->VGPR
|
||||
// copies.
|
||||
MRI.clearKillFlags(Fold.OpToFold->getReg());
|
||||
}
|
||||
DEBUG(dbgs() << "Folded source from " << MI << " into OpNo " <<
|
||||
static_cast<int>(Fold.UseOpNo) << " of " << *Fold.UseMI << '\n');
|
||||
|
||||
// Folding the immediate may reveal operations that can be constant
|
||||
// folded or replaced with a copy. This can happen for example after
|
||||
// frame indices are lowered to constants or from splitting 64-bit
|
||||
// constants.
|
||||
tryConstantFoldOp(MRI, TII, Fold.UseMI);
|
||||
}
|
||||
}
|
||||
foldInstOperand(MI, OpToFold);
|
||||
}
|
||||
}
|
||||
return false;
|
||||
|
||||
858
test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
Normal file
858
test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
Normal file
@ -0,0 +1,858 @@
|
||||
# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=hawaii -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination -o - %s | FileCheck -check-prefix=GCN %s
|
||||
--- |
|
||||
define void @s_fold_and_imm_regimm_32(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
|
||||
%and = and i32 %a, 1234567
|
||||
store volatile i32 %and, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @v_fold_and_imm_regimm_32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%idxprom = sext i32 %tid to i64
|
||||
%gep.a = getelementptr i32, i32 addrspace(1)* %aptr, i64 %idxprom
|
||||
%gep.out = getelementptr i32, i32 addrspace(1)* %out, i64 %idxprom
|
||||
%a = load i32, i32 addrspace(1)* %gep.a
|
||||
%and = and i32 %a, 1234567
|
||||
store i32 %and, i32 addrspace(1)* %gep.out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @s_fold_shl_imm_regimm_32(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
|
||||
%shl = shl i32 %a, 12
|
||||
store volatile i32 %shl, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @v_fold_shl_imm_regimm_32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%idxprom = sext i32 %tid to i64
|
||||
%gep.a = getelementptr i32, i32 addrspace(1)* %aptr, i64 %idxprom
|
||||
%gep.out = getelementptr i32, i32 addrspace(1)* %out, i64 %idxprom
|
||||
%a = load i32, i32 addrspace(1)* %gep.a
|
||||
%shl = shl i32 %a, 12
|
||||
store i32 %shl, i32 addrspace(1)* %gep.out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @s_fold_ashr_imm_regimm_32(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
|
||||
%ashr = ashr i32 %a, 12
|
||||
store volatile i32 %ashr, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @v_fold_ashr_imm_regimm_32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%idxprom = sext i32 %tid to i64
|
||||
%gep.a = getelementptr i32, i32 addrspace(1)* %aptr, i64 %idxprom
|
||||
%gep.out = getelementptr i32, i32 addrspace(1)* %out, i64 %idxprom
|
||||
%a = load i32, i32 addrspace(1)* %gep.a
|
||||
%ashr = ashr i32 %a, 12
|
||||
store i32 %ashr, i32 addrspace(1)* %gep.out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @s_fold_lshr_imm_regimm_32(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
|
||||
%lshr = lshr i32 %a, 12
|
||||
store volatile i32 %lshr, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @v_fold_lshr_imm_regimm_32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%idxprom = sext i32 %tid to i64
|
||||
%gep.a = getelementptr i32, i32 addrspace(1)* %aptr, i64 %idxprom
|
||||
%gep.out = getelementptr i32, i32 addrspace(1)* %out, i64 %idxprom
|
||||
%a = load i32, i32 addrspace(1)* %gep.a
|
||||
%lshr = lshr i32 %a, 12
|
||||
store i32 %lshr, i32 addrspace(1)* %gep.out
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readnone }
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
# GCN-LABEL: name: s_fold_and_imm_regimm_32{{$}}
|
||||
# GCN: %10 = V_MOV_B32_e32 1543, implicit %exec
|
||||
# GCN: BUFFER_STORE_DWORD_OFFSET killed %10,
|
||||
name: s_fold_and_imm_regimm_32
|
||||
alignment: 0
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: sgpr_64 }
|
||||
- { id: 1, class: sreg_64_xexec }
|
||||
- { id: 2, class: sreg_32_xm0 }
|
||||
- { id: 3, class: sreg_32_xm0 }
|
||||
- { id: 4, class: sreg_32_xm0 }
|
||||
- { id: 5, class: sreg_32_xm0 }
|
||||
- { id: 6, class: sreg_128 }
|
||||
- { id: 7, class: sreg_32_xm0 }
|
||||
- { id: 8, class: sreg_32_xm0 }
|
||||
- { id: 9, class: sreg_32_xm0 }
|
||||
- { id: 10, class: vgpr_32 }
|
||||
liveins:
|
||||
- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 0
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
liveins: %sgpr0_sgpr1
|
||||
|
||||
%0 = COPY %sgpr0_sgpr1
|
||||
%1 = S_LOAD_DWORDX2_IMM %0, 36, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
|
||||
%2 = COPY %1.sub1
|
||||
%3 = COPY %1.sub0
|
||||
%4 = S_MOV_B32 61440
|
||||
%5 = S_MOV_B32 -1
|
||||
%6 = REG_SEQUENCE killed %2, 1, killed %3, 2, killed %4, 3, killed %5, 4
|
||||
%7 = S_MOV_B32 1234567
|
||||
%8 = S_MOV_B32 9999
|
||||
%9 = S_AND_B32 killed %7, killed %8, implicit-def dead %scc
|
||||
%10 = COPY %9
|
||||
BUFFER_STORE_DWORD_OFFSET killed %10, killed %6, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into %ir.out)
|
||||
S_ENDPGM
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
# GCN-LABEL: name: v_fold_and_imm_regimm_32{{$}}
|
||||
|
||||
# GCN: %9 = V_MOV_B32_e32 646, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %19, %9,
|
||||
|
||||
# GCN: %10 = V_MOV_B32_e32 646, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %19, %10
|
||||
|
||||
# GCN: %11 = V_MOV_B32_e32 646, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %19, %11,
|
||||
|
||||
# GCN: %12 = V_MOV_B32_e32 1234567, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %19, %12,
|
||||
|
||||
# GCN: %13 = V_MOV_B32_e32 63, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %19, %13,
|
||||
|
||||
name: v_fold_and_imm_regimm_32
|
||||
alignment: 0
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: sgpr_64 }
|
||||
- { id: 1, class: sreg_32_xm0 }
|
||||
- { id: 2, class: sgpr_32 }
|
||||
- { id: 3, class: vgpr_32 }
|
||||
- { id: 4, class: sreg_64_xexec }
|
||||
- { id: 20, class: sreg_32_xm0 }
|
||||
- { id: 24, class: vgpr_32 }
|
||||
- { id: 25, class: vreg_64 }
|
||||
- { id: 26, class: sreg_32_xm0 }
|
||||
- { id: 27, class: vgpr_32 }
|
||||
- { id: 28, class: vgpr_32 }
|
||||
- { id: 29, class: vgpr_32 }
|
||||
- { id: 30, class: vgpr_32 }
|
||||
- { id: 31, class: vgpr_32 }
|
||||
- { id: 32, class: vreg_64 }
|
||||
- { id: 33, class: vreg_64 }
|
||||
- { id: 34, class: vgpr_32 }
|
||||
- { id: 35, class: vgpr_32 }
|
||||
- { id: 36, class: vgpr_32 }
|
||||
- { id: 37, class: vreg_64 }
|
||||
- { id: 44, class: vgpr_32 }
|
||||
|
||||
liveins:
|
||||
- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
|
||||
- { reg: '%vgpr0', virtual-reg: '%3' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 0
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
liveins: %sgpr0_sgpr1, %vgpr0
|
||||
|
||||
%3 = COPY %vgpr0
|
||||
%0 = COPY %sgpr0_sgpr1
|
||||
%4 = S_LOAD_DWORDX2_IMM %0, 36, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
|
||||
%31 = V_ASHRREV_I32_e64 31, %3, implicit %exec
|
||||
%32 = REG_SEQUENCE %3, 1, %31, 2
|
||||
%33 = V_LSHLREV_B64 2, killed %32, implicit %exec
|
||||
%20 = COPY %4.sub1
|
||||
%44 = V_ADD_I32_e32 %4.sub0, %33.sub0, implicit-def %vcc, implicit %exec
|
||||
%36 = COPY killed %20
|
||||
%35 = V_ADDC_U32_e32 %33.sub1, %36, implicit-def %vcc, implicit %vcc, implicit %exec
|
||||
%37 = REG_SEQUENCE %44, 1, killed %35, 2
|
||||
%24 = V_MOV_B32_e32 982, implicit %exec
|
||||
%26 = S_MOV_B32 1234567
|
||||
%34 = V_MOV_B32_e32 63, implicit %exec
|
||||
|
||||
%27 = V_AND_B32_e64 %26, %24, implicit %exec
|
||||
FLAT_STORE_DWORD %37, %27, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%28 = V_AND_B32_e64 %24, %26, implicit %exec
|
||||
FLAT_STORE_DWORD %37, %28, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%29 = V_AND_B32_e32 %26, %24, implicit %exec
|
||||
FLAT_STORE_DWORD %37, %29, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%30 = V_AND_B32_e64 %26, %26, implicit %exec
|
||||
FLAT_STORE_DWORD %37, %30, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%31 = V_AND_B32_e64 %34, %34, implicit %exec
|
||||
FLAT_STORE_DWORD %37, %31, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
S_ENDPGM
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
# GCN-LABEL: name: s_fold_shl_imm_regimm_32{{$}}
|
||||
# GC1: %13 = V_MOV_B32_e32 4096, implicit %exec
|
||||
# GCN: BUFFER_STORE_DWORD_OFFSET killed %13,
|
||||
|
||||
name: s_fold_shl_imm_regimm_32
|
||||
alignment: 0
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: sgpr_64 }
|
||||
- { id: 1, class: sreg_32_xm0 }
|
||||
- { id: 2, class: sgpr_32 }
|
||||
- { id: 3, class: vgpr_32 }
|
||||
- { id: 4, class: sreg_64_xexec }
|
||||
- { id: 5, class: sreg_32_xm0_xexec }
|
||||
- { id: 6, class: sreg_32_xm0 }
|
||||
- { id: 7, class: sreg_32_xm0 }
|
||||
- { id: 8, class: sreg_32_xm0 }
|
||||
- { id: 9, class: sreg_32_xm0 }
|
||||
- { id: 10, class: sreg_128 }
|
||||
- { id: 11, class: sreg_32_xm0 }
|
||||
- { id: 12, class: sreg_32_xm0 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
liveins:
|
||||
- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 0
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
liveins: %sgpr0_sgpr1
|
||||
|
||||
%0 = COPY %sgpr0_sgpr1
|
||||
%4 = S_LOAD_DWORDX2_IMM %0, 36, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
|
||||
%5 = S_MOV_B32 1
|
||||
%6 = COPY %4.sub1
|
||||
%7 = COPY %4.sub0
|
||||
%8 = S_MOV_B32 61440
|
||||
%9 = S_MOV_B32 -1
|
||||
%10 = REG_SEQUENCE killed %7, 1, killed %6, 2, killed %9, 3, killed %8, 4
|
||||
%12 = S_LSHL_B32 killed %5, 12, implicit-def dead %scc
|
||||
%13 = COPY %12
|
||||
BUFFER_STORE_DWORD_OFFSET killed %13, killed %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into %ir.out)
|
||||
S_ENDPGM
|
||||
|
||||
...
|
||||
---
|
||||
# GCN-LABEL: name: v_fold_shl_imm_regimm_32{{$}}
|
||||
|
||||
# GCN: %11 = V_MOV_B32_e32 40955904, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %11,
|
||||
|
||||
# GCN: %12 = V_MOV_B32_e32 24, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %12,
|
||||
|
||||
# GCN: %13 = V_MOV_B32_e32 4096, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %13,
|
||||
|
||||
# GCN: %14 = V_MOV_B32_e32 24, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %14,
|
||||
|
||||
# GCN: %15 = V_MOV_B32_e32 0, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %15,
|
||||
|
||||
# GCN: %22 = V_MOV_B32_e32 4096, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %22,
|
||||
|
||||
# GCN: %23 = V_MOV_B32_e32 1, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %23,
|
||||
|
||||
# GCN: %25 = V_MOV_B32_e32 2, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %25,
|
||||
|
||||
# GCN: %26 = V_MOV_B32_e32 7927808, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %26,
|
||||
|
||||
# GCN: %28 = V_MOV_B32_e32 -8, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %28,
|
||||
|
||||
name: v_fold_shl_imm_regimm_32
|
||||
alignment: 0
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: sgpr_64 }
|
||||
- { id: 1, class: sreg_32_xm0 }
|
||||
- { id: 2, class: vgpr_32 }
|
||||
- { id: 3, class: sreg_64_xexec }
|
||||
- { id: 4, class: sreg_64_xexec }
|
||||
- { id: 5, class: sreg_32_xm0 }
|
||||
- { id: 6, class: vgpr_32 }
|
||||
- { id: 7, class: sreg_32_xm0 }
|
||||
- { id: 8, class: sreg_64 }
|
||||
- { id: 9, class: sreg_32_xm0 }
|
||||
- { id: 10, class: vgpr_32 }
|
||||
- { id: 11, class: vgpr_32 }
|
||||
- { id: 12, class: vgpr_32 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
- { id: 14, class: vgpr_32 }
|
||||
- { id: 15, class: vgpr_32 }
|
||||
- { id: 16, class: vreg_64 }
|
||||
- { id: 17, class: vreg_64 }
|
||||
- { id: 18, class: vgpr_32 }
|
||||
- { id: 19, class: vgpr_32 }
|
||||
- { id: 20, class: vreg_64 }
|
||||
- { id: 21, class: vgpr_32 }
|
||||
- { id: 22, class: vgpr_32 }
|
||||
- { id: 23, class: vgpr_32 }
|
||||
- { id: 24, class: vgpr_32 }
|
||||
- { id: 25, class: vgpr_32 }
|
||||
- { id: 26, class: vgpr_32 }
|
||||
- { id: 27, class: sreg_32_xm0 }
|
||||
- { id: 28, class: vgpr_32 }
|
||||
liveins:
|
||||
- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
|
||||
- { reg: '%vgpr0', virtual-reg: '%2' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 0
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
liveins: %sgpr0_sgpr1, %vgpr0
|
||||
|
||||
%2 = COPY %vgpr0
|
||||
%0 = COPY %sgpr0_sgpr1
|
||||
%3 = S_LOAD_DWORDX2_IMM %0, 36, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
|
||||
%15 = V_ASHRREV_I32_e64 31, %2, implicit %exec
|
||||
%16 = REG_SEQUENCE %2, 1, %15, 2
|
||||
%17 = V_LSHLREV_B64 2, killed %16, implicit %exec
|
||||
%9 = COPY %3.sub1
|
||||
%21 = V_ADD_I32_e32 %3.sub0, %17.sub0, implicit-def %vcc, implicit %exec
|
||||
%19 = COPY killed %9
|
||||
%18 = V_ADDC_U32_e32 %17.sub1, %19, implicit-def %vcc, implicit %vcc, implicit %exec
|
||||
%20 = REG_SEQUENCE %21, 1, killed %18, 2
|
||||
%10 = V_MOV_B32_e32 9999, implicit %exec
|
||||
%24 = V_MOV_B32_e32 3871, implicit %exec
|
||||
%6 = V_MOV_B32_e32 1, implicit %exec
|
||||
%7 = S_MOV_B32 1
|
||||
%27 = S_MOV_B32 -4
|
||||
|
||||
%11 = V_LSHLREV_B32_e64 12, %10, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %11, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%12 = V_LSHLREV_B32_e64 %7, 12, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %12, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%13 = V_LSHL_B32_e64 %7, 12, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %13, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%14 = V_LSHL_B32_e64 12, %7, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %14, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%15 = V_LSHL_B32_e64 12, %24, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %15, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%22 = V_LSHL_B32_e64 %6, 12, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %22, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%23 = V_LSHL_B32_e64 %6, 32, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %23, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%25 = V_LSHL_B32_e32 %6, %6, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %25, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%26 = V_LSHLREV_B32_e32 11, %24, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%28 = V_LSHL_B32_e32 %27, %6, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
S_ENDPGM
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
# GCN-LABEL: name: s_fold_ashr_imm_regimm_32{{$}}
|
||||
# GCN: %11 = V_MOV_B32_e32 243, implicit %exec
|
||||
# GCN: BUFFER_STORE_DWORD_OFFSET killed %11, killed %8,
|
||||
name: s_fold_ashr_imm_regimm_32
|
||||
alignment: 0
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: sgpr_64 }
|
||||
- { id: 1, class: sreg_32_xm0 }
|
||||
- { id: 4, class: sreg_64_xexec }
|
||||
- { id: 5, class: sreg_32_xm0_xexec }
|
||||
- { id: 6, class: sreg_32_xm0 }
|
||||
- { id: 7, class: sreg_32_xm0 }
|
||||
- { id: 8, class: sreg_32_xm0 }
|
||||
- { id: 9, class: sreg_32_xm0 }
|
||||
- { id: 10, class: sreg_128 }
|
||||
- { id: 11, class: sreg_32_xm0 }
|
||||
- { id: 12, class: sreg_32_xm0 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
liveins:
|
||||
- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 0
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
liveins: %sgpr0_sgpr1
|
||||
|
||||
%0 = COPY %sgpr0_sgpr1
|
||||
%4 = S_LOAD_DWORDX2_IMM %0, 36, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
|
||||
%5 = S_MOV_B32 999123
|
||||
%6 = COPY %4.sub1
|
||||
%7 = COPY %4.sub0
|
||||
%8 = S_MOV_B32 61440
|
||||
%9 = S_MOV_B32 -1
|
||||
%10 = REG_SEQUENCE killed %7, 1, killed %6, 2, killed %9, 3, killed %8, 4
|
||||
%12 = S_ASHR_I32 killed %5, 12, implicit-def dead %scc
|
||||
%13 = COPY %12
|
||||
BUFFER_STORE_DWORD_OFFSET killed %13, killed %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into %ir.out)
|
||||
S_ENDPGM
|
||||
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: v_fold_ashr_imm_regimm_32{{$}}
|
||||
# GCN: %11 = V_MOV_B32_e32 3903258, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %11,
|
||||
|
||||
# GCN: %12 = V_MOV_B32_e32 62452139, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %12,
|
||||
|
||||
# GCN: %13 = V_MOV_B32_e32 1678031, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %13,
|
||||
|
||||
# GCN: %14 = V_MOV_B32_e32 3, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %14,
|
||||
|
||||
# GCN: %15 = V_MOV_B32_e32 -1, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %15,
|
||||
|
||||
# GCN: %22 = V_MOV_B32_e32 62500, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %22,
|
||||
|
||||
# GCN: %23 = V_MOV_B32_e32 500000, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %23,
|
||||
|
||||
# GCN: %25 = V_MOV_B32_e32 1920, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %25,
|
||||
|
||||
# GCN: %26 = V_MOV_B32_e32 487907, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %26,
|
||||
|
||||
# GCN: %28 = V_MOV_B32_e32 -1, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %28,
|
||||
|
||||
name: v_fold_ashr_imm_regimm_32
|
||||
alignment: 0
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: sgpr_64 }
|
||||
- { id: 1, class: sreg_32_xm0 }
|
||||
- { id: 2, class: vgpr_32 }
|
||||
- { id: 3, class: sreg_64_xexec }
|
||||
- { id: 4, class: sreg_64_xexec }
|
||||
- { id: 5, class: sreg_32_xm0 }
|
||||
- { id: 6, class: vgpr_32 }
|
||||
- { id: 7, class: sreg_32_xm0 }
|
||||
- { id: 8, class: sreg_32_xm0 }
|
||||
- { id: 9, class: sreg_32_xm0 }
|
||||
- { id: 10, class: vgpr_32 }
|
||||
- { id: 11, class: vgpr_32 }
|
||||
- { id: 12, class: vgpr_32 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
- { id: 14, class: vgpr_32 }
|
||||
- { id: 15, class: vgpr_32 }
|
||||
- { id: 16, class: vreg_64 }
|
||||
- { id: 17, class: vreg_64 }
|
||||
- { id: 18, class: vgpr_32 }
|
||||
- { id: 19, class: vgpr_32 }
|
||||
- { id: 20, class: vreg_64 }
|
||||
- { id: 21, class: vgpr_32 }
|
||||
- { id: 22, class: vgpr_32 }
|
||||
- { id: 23, class: vgpr_32 }
|
||||
- { id: 24, class: vgpr_32 }
|
||||
- { id: 25, class: vgpr_32 }
|
||||
- { id: 26, class: vgpr_32 }
|
||||
- { id: 27, class: sreg_32_xm0 }
|
||||
- { id: 28, class: vgpr_32 }
|
||||
- { id: 32, class: sreg_32_xm0 }
|
||||
- { id: 33, class: sreg_32_xm0 }
|
||||
- { id: 34, class: vgpr_32 }
|
||||
- { id: 35, class: vgpr_32 }
|
||||
liveins:
|
||||
- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
|
||||
- { reg: '%vgpr0', virtual-reg: '%2' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 0
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
liveins: %sgpr0_sgpr1, %vgpr0
|
||||
|
||||
%2 = COPY %vgpr0
|
||||
%0 = COPY %sgpr0_sgpr1
|
||||
%3 = S_LOAD_DWORDX2_IMM %0, 36, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
|
||||
%15 = V_ASHRREV_I32_e64 31, %2, implicit %exec
|
||||
%16 = REG_SEQUENCE %2, 1, %15, 2
|
||||
%17 = V_LSHLREV_B64 2, killed %16, implicit %exec
|
||||
%9 = COPY %3.sub1
|
||||
%21 = V_ADD_I32_e32 %3.sub0, %17.sub0, implicit-def %vcc, implicit %exec
|
||||
%19 = COPY killed %9
|
||||
%18 = V_ADDC_U32_e32 %17.sub1, %19, implicit-def %vcc, implicit %vcc, implicit %exec
|
||||
%20 = REG_SEQUENCE %21, 1, killed %18, 2
|
||||
%10 = V_MOV_B32_e32 999234234, implicit %exec
|
||||
%24 = V_MOV_B32_e32 3871, implicit %exec
|
||||
%6 = V_MOV_B32_e32 1000000, implicit %exec
|
||||
%7 = S_MOV_B32 13424252
|
||||
%8 = S_MOV_B32 4
|
||||
%27 = S_MOV_B32 -4
|
||||
%32 = S_MOV_B32 1
|
||||
%33 = S_MOV_B32 3841
|
||||
%34 = V_MOV_B32_e32 3841, implicit %exec
|
||||
%35 = V_MOV_B32_e32 2, implicit %exec
|
||||
|
||||
%11 = V_ASHRREV_I32_e64 8, %10, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %11, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%12 = V_ASHRREV_I32_e64 %8, %10, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %12, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%13 = V_ASHR_I32_e64 %7, 3, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %13, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%14 = V_ASHR_I32_e64 7, %32, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %14, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%15 = V_ASHR_I32_e64 %27, %24, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %15, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%22 = V_ASHR_I32_e64 %6, 4, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %22, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%23 = V_ASHR_I32_e64 %6, %33, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %23, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%25 = V_ASHR_I32_e32 %34, %34, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %25, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%26 = V_ASHRREV_I32_e32 11, %10, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%28 = V_ASHR_I32_e32 %27, %35, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
S_ENDPGM
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
# GCN-LABEL: name: s_fold_lshr_imm_regimm_32{{$}}
|
||||
# GCN: %11 = V_MOV_B32_e32 1048332, implicit %exec
|
||||
# GCN: BUFFER_STORE_DWORD_OFFSET killed %11, killed %8,
|
||||
name: s_fold_lshr_imm_regimm_32
|
||||
alignment: 0
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: sgpr_64 }
|
||||
- { id: 1, class: sreg_32_xm0 }
|
||||
- { id: 4, class: sreg_64_xexec }
|
||||
- { id: 5, class: sreg_32_xm0_xexec }
|
||||
- { id: 6, class: sreg_32_xm0 }
|
||||
- { id: 7, class: sreg_32_xm0 }
|
||||
- { id: 8, class: sreg_32_xm0 }
|
||||
- { id: 9, class: sreg_32_xm0 }
|
||||
- { id: 10, class: sreg_128 }
|
||||
- { id: 11, class: sreg_32_xm0 }
|
||||
- { id: 12, class: sreg_32_xm0 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
liveins:
|
||||
- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 0
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
liveins: %sgpr0_sgpr1
|
||||
|
||||
%0 = COPY %sgpr0_sgpr1
|
||||
%4 = S_LOAD_DWORDX2_IMM %0, 36, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
|
||||
%5 = S_MOV_B32 -999123
|
||||
%6 = COPY %4.sub1
|
||||
%7 = COPY %4.sub0
|
||||
%8 = S_MOV_B32 61440
|
||||
%9 = S_MOV_B32 -1
|
||||
%10 = REG_SEQUENCE killed %7, 1, killed %6, 2, killed %9, 3, killed %8, 4
|
||||
%12 = S_LSHR_B32 killed %5, 12, implicit-def dead %scc
|
||||
%13 = COPY %12
|
||||
BUFFER_STORE_DWORD_OFFSET killed %13, killed %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into %ir.out)
|
||||
S_ENDPGM
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
# GCN-LABEL: name: v_fold_lshr_imm_regimm_32{{$}}
|
||||
# GCN: %11 = V_MOV_B32_e32 3903258, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %11,
|
||||
|
||||
# GCN: %12 = V_MOV_B32_e32 62452139, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %12,
|
||||
|
||||
# GCN: %13 = V_MOV_B32_e32 1678031, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %13,
|
||||
|
||||
# GCN: %14 = V_MOV_B32_e32 3, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %14,
|
||||
|
||||
# GCN: %15 = V_MOV_B32_e32 1, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %15,
|
||||
|
||||
# GCN: %22 = V_MOV_B32_e32 62500, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %22,
|
||||
|
||||
# GCN: %23 = V_MOV_B32_e32 500000, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %23,
|
||||
|
||||
# GCN: %25 = V_MOV_B32_e32 1920, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %25,
|
||||
|
||||
# GCN: %26 = V_MOV_B32_e32 487907, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %26,
|
||||
|
||||
# GCN: %28 = V_MOV_B32_e32 1073741823, implicit %exec
|
||||
# GCN: FLAT_STORE_DWORD %20, %28,
|
||||
|
||||
name: v_fold_lshr_imm_regimm_32
|
||||
alignment: 0
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: sgpr_64 }
|
||||
- { id: 1, class: sreg_32_xm0 }
|
||||
- { id: 2, class: vgpr_32 }
|
||||
- { id: 3, class: sreg_64_xexec }
|
||||
- { id: 4, class: sreg_64_xexec }
|
||||
- { id: 5, class: sreg_32_xm0 }
|
||||
- { id: 6, class: vgpr_32 }
|
||||
- { id: 7, class: sreg_32_xm0 }
|
||||
- { id: 8, class: sreg_32_xm0 }
|
||||
- { id: 9, class: sreg_32_xm0 }
|
||||
- { id: 10, class: vgpr_32 }
|
||||
- { id: 11, class: vgpr_32 }
|
||||
- { id: 12, class: vgpr_32 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
- { id: 14, class: vgpr_32 }
|
||||
- { id: 15, class: vgpr_32 }
|
||||
- { id: 16, class: vreg_64 }
|
||||
- { id: 17, class: vreg_64 }
|
||||
- { id: 18, class: vgpr_32 }
|
||||
- { id: 19, class: vgpr_32 }
|
||||
- { id: 20, class: vreg_64 }
|
||||
- { id: 21, class: vgpr_32 }
|
||||
- { id: 22, class: vgpr_32 }
|
||||
- { id: 23, class: vgpr_32 }
|
||||
- { id: 24, class: vgpr_32 }
|
||||
- { id: 25, class: vgpr_32 }
|
||||
- { id: 26, class: vgpr_32 }
|
||||
- { id: 27, class: sreg_32_xm0 }
|
||||
- { id: 28, class: vgpr_32 }
|
||||
- { id: 32, class: sreg_32_xm0 }
|
||||
- { id: 33, class: sreg_32_xm0 }
|
||||
- { id: 34, class: vgpr_32 }
|
||||
- { id: 35, class: vgpr_32 }
|
||||
liveins:
|
||||
- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
|
||||
- { reg: '%vgpr0', virtual-reg: '%2' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 0
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
liveins: %sgpr0_sgpr1, %vgpr0
|
||||
|
||||
%2 = COPY %vgpr0
|
||||
%0 = COPY %sgpr0_sgpr1
|
||||
%3 = S_LOAD_DWORDX2_IMM %0, 36, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
|
||||
%15 = V_ASHRREV_I32_e64 31, %2, implicit %exec
|
||||
%16 = REG_SEQUENCE %2, 1, %15, 2
|
||||
%17 = V_LSHLREV_B64 2, killed %16, implicit %exec
|
||||
%9 = COPY %3.sub1
|
||||
%21 = V_ADD_I32_e32 %3.sub0, %17.sub0, implicit-def %vcc, implicit %exec
|
||||
%19 = COPY killed %9
|
||||
%18 = V_ADDC_U32_e32 %17.sub1, %19, implicit-def %vcc, implicit %vcc, implicit %exec
|
||||
%20 = REG_SEQUENCE %21, 1, killed %18, 2
|
||||
%10 = V_MOV_B32_e32 999234234, implicit %exec
|
||||
%24 = V_MOV_B32_e32 3871, implicit %exec
|
||||
%6 = V_MOV_B32_e32 1000000, implicit %exec
|
||||
%7 = S_MOV_B32 13424252
|
||||
%8 = S_MOV_B32 4
|
||||
%27 = S_MOV_B32 -4
|
||||
%32 = S_MOV_B32 1
|
||||
%33 = S_MOV_B32 3841
|
||||
%34 = V_MOV_B32_e32 3841, implicit %exec
|
||||
%35 = V_MOV_B32_e32 2, implicit %exec
|
||||
|
||||
%11 = V_LSHRREV_B32_e64 8, %10, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %11, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%12 = V_LSHRREV_B32_e64 %8, %10, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %12, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%13 = V_LSHR_B32_e64 %7, 3, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %13, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%14 = V_LSHR_B32_e64 7, %32, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %14, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%15 = V_LSHR_B32_e64 %27, %24, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %15, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%22 = V_LSHR_B32_e64 %6, 4, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %22, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%23 = V_LSHR_B32_e64 %6, %33, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %23, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%25 = V_LSHR_B32_e32 %34, %34, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %25, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%26 = V_LSHRREV_B32_e32 11, %10, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%28 = V_LSHR_B32_e32 %27, %35, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
S_ENDPGM
|
||||
|
||||
...
|
||||
Loading…
x
Reference in New Issue
Block a user