RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-02-19 03:38:26 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Expand PPC64 atomic load and store

Browse Source 
Use of store or load with the atomic specifier on 64-bit types would
cause instruction-selection failures. As with the 32-bit case, these
can use the default expansion in terms of cmp-and-swap.

llvm-svn: 171072
This commit is contained in:
Hal Finkel 2012-12-25 17:22:53 +00:00
parent f41a8d635d
commit 6b98f1baa2
2 changed files with 22 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -443,6 +443,8 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
setBooleanContents(ZeroOrOneBooleanContent);
setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?

20
test/CodeGen/PowerPC/atomic-2.ll
View File

@ -24,3 +24,23 @@ define i64 @exchange(i64* %mem, i64 %val) nounwind {
; CHECK: stdcx.
ret i64 %tmp
}
define void @atomic_store(i64* %mem, i64 %val) nounwind {
entry:
; CHECK: @atomic_store
store atomic i64 %val, i64* %mem release, align 64
; CHECK: ldarx
; CHECK: stdcx.
ret void
}
define i64 @atomic_load(i64* %mem) nounwind {
entry:
; CHECK: @atomic_load
%tmp = load atomic i64* %mem acquire, align 64
; CHECK: ldarx
; CHECK: stdcx.
; CHECK: stdcx.
ret i64 %tmp
}