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Add load and other support to the dag-dag isel. Patch contributed by Evan
Cheng! llvm-svn: 24419
This commit is contained in:
Chris Lattner
parent
89056c7145
commit
6e0171ba8b
@ -15,6 +15,8 @@
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#include "X86.h"
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#include "X86Subtarget.h"
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#include "X86ISelLowering.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetMachine.h"
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@ -26,6 +28,32 @@ using namespace llvm;
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// Pattern Matcher Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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/// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
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/// SDOperand's instead of register numbers for the leaves of the matched
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/// tree.
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struct X86ISelAddressMode {
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enum {
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RegBase,
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FrameIndexBase,
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} BaseType;
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struct { // This is really a union, discriminated by BaseType!
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SDOperand Reg;
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int FrameIndex;
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} Base;
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unsigned Scale;
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SDOperand IndexReg;
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unsigned Disp;
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GlobalValue *GV;
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X86ISelAddressMode()
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: BaseType(RegBase), Scale(1), IndexReg(), Disp(), GV(0) {
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}
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};
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}
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namespace {
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Statistic<>
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NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
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@ -66,6 +94,15 @@ namespace {
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private:
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SDOperand Select(SDOperand N);
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void SelectAddress(SDOperand N, X86ISelAddressMode &AM);
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bool MatchAddress(SDOperand N, X86ISelAddressMode &AM);
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/// getI8Imm - Return a target constant with the specified value, of type
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/// i8.
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inline SDOperand getI8Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i8);
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}
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/// getI16Imm - Return a target constant with the specified value, of type
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/// i16.
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inline SDOperand getI16Imm(unsigned Imm) {
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@ -93,6 +130,141 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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ScheduleAndEmitDAG(DAG);
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}
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/// SelectAddress - Pattern match the maximal addressing mode for this node.
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void X86DAGToDAGISel::SelectAddress(SDOperand N, X86ISelAddressMode &AM) {
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MatchAddress(N, AM);
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if (AM.BaseType == X86ISelAddressMode::RegBase && !AM.Base.Reg.Val) {
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AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
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} else {
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AM.Base.Reg = Select(AM.Base.Reg);
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}
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if (!AM.IndexReg.Val) {
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AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
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} else {
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AM.IndexReg = Select(AM.IndexReg);
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}
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}
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/// FIXME: copied from X86ISelPattern.cpp
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/// MatchAddress - Add the specified node to the specified addressing mode,
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/// returning true if it cannot be done. This just pattern matches for the
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/// addressing mode
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bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM) {
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switch (N.getOpcode()) {
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default: break;
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case ISD::FrameIndex:
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if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
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AM.BaseType = X86ISelAddressMode::FrameIndexBase;
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AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
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return false;
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}
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break;
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case ISD::GlobalAddress:
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if (AM.GV == 0) {
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GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
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// For Darwin, external and weak symbols are indirect, so we want to load
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// the value at address GV, not the value of GV itself. This means that
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// the GlobalAddress must be in the base or index register of the address,
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// not the GV offset field.
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if (Subtarget->getIndirectExternAndWeakGlobals() &&
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(GV->hasWeakLinkage() || GV->isExternal())) {
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break;
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} else {
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AM.GV = GV;
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return false;
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}
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}
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break;
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case ISD::Constant:
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AM.Disp += cast<ConstantSDNode>(N)->getValue();
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return false;
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case ISD::SHL:
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if (AM.IndexReg.Val == 0 && AM.Scale == 1)
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
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unsigned Val = CN->getValue();
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if (Val == 1 || Val == 2 || Val == 3) {
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AM.Scale = 1 << Val;
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SDOperand ShVal = N.Val->getOperand(0);
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// Okay, we know that we have a scale by now. However, if the scaled
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// value is an add of something and a constant, we can fold the
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// constant into the disp field here.
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if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
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isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
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AM.IndexReg = ShVal.Val->getOperand(0);
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ConstantSDNode *AddVal =
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cast<ConstantSDNode>(ShVal.Val->getOperand(1));
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AM.Disp += AddVal->getValue() << Val;
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} else {
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AM.IndexReg = ShVal;
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}
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return false;
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}
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}
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break;
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case ISD::MUL:
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// X*[3,5,9] -> X+X*[2,4,8]
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if (AM.IndexReg.Val == 0 && AM.BaseType == X86ISelAddressMode::RegBase &&
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AM.Base.Reg.Val == 0)
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1)))
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if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
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AM.Scale = unsigned(CN->getValue())-1;
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SDOperand MulVal = N.Val->getOperand(0);
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SDOperand Reg;
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// Okay, we know that we have a scale by now. However, if the scaled
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// value is an add of something and a constant, we can fold the
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// constant into the disp field here.
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if (MulVal.Val->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
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isa<ConstantSDNode>(MulVal.Val->getOperand(1))) {
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Reg = MulVal.Val->getOperand(0);
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ConstantSDNode *AddVal =
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cast<ConstantSDNode>(MulVal.Val->getOperand(1));
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AM.Disp += AddVal->getValue() * CN->getValue();
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} else {
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Reg = N.Val->getOperand(0);
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}
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AM.IndexReg = AM.Base.Reg = Reg;
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return false;
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}
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break;
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case ISD::ADD: {
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X86ISelAddressMode Backup = AM;
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if (!MatchAddress(N.Val->getOperand(0), AM) &&
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!MatchAddress(N.Val->getOperand(1), AM))
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return false;
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AM = Backup;
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if (!MatchAddress(N.Val->getOperand(1), AM) &&
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!MatchAddress(N.Val->getOperand(0), AM))
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return false;
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AM = Backup;
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break;
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}
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}
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// Is the base register already occupied?
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if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
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// If so, check to see if the scale index register is set.
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if (AM.IndexReg.Val == 0) {
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AM.IndexReg = N;
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AM.Scale = 1;
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return false;
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}
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// Otherwise, we cannot select it.
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return true;
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}
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// Default, generate it as a register.
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AM.BaseType = X86ISelAddressMode::RegBase;
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AM.Base.Reg = N;
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return false;
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}
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SDOperand X86DAGToDAGISel::Select(SDOperand Op) {
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SDNode *N = Op.Val;
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MVT::ValueType OpVT = Op.getValueType();
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@ -103,6 +275,21 @@ SDOperand X86DAGToDAGISel::Select(SDOperand Op) {
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switch (N->getOpcode()) {
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default: break;
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case ISD::SHL:
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
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if (CN->getValue() == 1) { // X = SHL Y, 1 -> X = ADD Y, Y
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switch (OpVT) {
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default: assert(0 && "Cannot shift this type!");
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case MVT::i8: Opc = X86::ADD8rr; break;
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case MVT::i16: Opc = X86::ADD16rr; break;
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case MVT::i32: Opc = X86::ADD32rr; break;
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}
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SDOperand Tmp0 = Select(N->getOperand(0));
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CurDAG->SelectNodeTo(N, Opc, MVT::i32, Tmp0, Tmp0);
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return SDOperand(N, 0);
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}
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}
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case ISD::RET: {
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SDOperand Chain = Select(N->getOperand(0)); // Token chain.
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switch (N->getNumOperands()) {
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@ -131,11 +318,47 @@ SDOperand X86DAGToDAGISel::Select(SDOperand Op) {
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if (X86Lowering.getBytesToPopOnReturn() == 0)
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CurDAG->SelectNodeTo(N, X86::RET, MVT::Other, Chain);
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else
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CurDAG->SelectNodeTo(N, X86::RET, MVT::Other, Chain,
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getI16Imm(X86Lowering.getBytesToPopOnReturn()));
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CurDAG->SelectNodeTo(N, X86::RET, MVT::Other,
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getI16Imm(X86Lowering.getBytesToPopOnReturn()),
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Chain);
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return SDOperand(N, 0);
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}
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case ISD::LOAD: {
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switch (N->getValueType(0)) {
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default: assert(0 && "Cannot load this type!");
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case MVT::i1:
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case MVT::i8: Opc = X86::MOV8rm; break;
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case MVT::i16: Opc = X86::MOV16rm; break;
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case MVT::i32: Opc = X86::MOV32rm; break;
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case MVT::f32: Opc = X86::MOVSSrm; break;
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case MVT::f64: Opc = X86::FLD64m; ContainsFPCode = true; break;
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}
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if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N->getOperand(1))){
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unsigned CPIdx = BB->getParent()->getConstantPool()->
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getConstantPoolIndex(CP->get());
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// ???
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assert(0 && "Can't handle load from constant pool!");
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} else {
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SDOperand Chain = Select(N->getOperand(0)); // Token chain.
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X86ISelAddressMode AM;
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SelectAddress(N->getOperand(1), AM);
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SDOperand Scale = getI8Imm (AM.Scale);
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SDOperand Disp = AM.GV ? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32)
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: getI32Imm(AM.Disp);
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if (AM.BaseType == X86ISelAddressMode::RegBase) {
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CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
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AM.Base.Reg, Scale, AM.IndexReg, Disp, Chain);
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} else {
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SDOperand Base = CurDAG->getFrameIndex(AM.Base.FrameIndex, MVT::i32);
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CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
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Base, Scale, AM.IndexReg, Disp, Chain);
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}
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}
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return SDOperand(N, Op.ResNo);
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}
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}
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return SelectCode(Op);
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