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add proper encoding for MTCRF instead of using a hack.

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llvm-svn: 119121
This commit is contained in:
Chris Lattner 2010-11-15 05:19:25 +00:00
parent b2daeac125
commit 6eb2a0b277
3 changed files with 37 additions and 15 deletions
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31
lib/Target/PowerPC/PPCCodeEmitter.cpp
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@ -58,6 +58,8 @@ namespace {
unsigned getMachineOpValue(const MachineInstr &MI, unsigned getMachineOpValue(const MachineInstr &MI,
const MachineOperand &MO) const; const MachineOperand &MO) const;
unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const;
const char *getPassName() const { return "PowerPC Machine Code Emitter"; } const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
/// runOnMachineFunction - emits the given MachineFunction to memory /// runOnMachineFunction - emits the given MachineFunction to memory
@ -124,24 +126,29 @@ void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
} }
} }
unsigned PPCCodeEmitter::get_crbitm_encoding(const MachineInstr &MI,
unsigned OpNo) const {
const MachineOperand &MO = MI.getOperand(OpNo);
assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
(MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
return 0x80 >> PPCRegisterInfo::getRegisterNumbering(MO.getReg());
}
unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI, unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
const MachineOperand &MO) const { const MachineOperand &MO) const {
unsigned rv = 0; // Return value; defaults to 0 for unhandled cases unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
// or things that get fixed up later by the JIT. // or things that get fixed up later by the JIT.
if (MO.isReg()) { if (MO.isReg()) {
rv = PPCRegisterInfo::getRegisterNumbering(MO.getReg()); assert(MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF);
return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
// Special encoding for MTCRF and MFOCRF, which uses a bit mask for the }
// register, not the register number directly.
if ((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) && if (MO.isImm())
(MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)) { return MO.getImm();
rv = 0x80 >> rv;
} if (MO.isGlobal() || MO.isSymbol() || MO.isCPI() || MO.isJTI()) {
} else if (MO.isImm()) {
rv = MO.getImm();
} else if (MO.isGlobal() || MO.isSymbol() ||
MO.isCPI() || MO.isJTI()) {
unsigned Reloc = 0; unsigned Reloc = 0;
if (MI.getOpcode() == PPC::BL_Darwin || MI.getOpcode() == PPC::BL8_Darwin || if (MI.getOpcode() == PPC::BL_Darwin || MI.getOpcode() == PPC::BL8_Darwin ||
MI.getOpcode() == PPC::BL_SVR4 || MI.getOpcode() == PPC::BL8_ELF || MI.getOpcode() == PPC::BL_SVR4 || MI.getOpcode() == PPC::BL8_ELF ||

1
lib/Target/PowerPC/PPCInstrInfo.td
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@ -304,6 +304,7 @@ def symbolLo: Operand<i32> {
} }
def crbitm: Operand<i8> { def crbitm: Operand<i8> {
let PrintMethod = "printcrbitm"; let PrintMethod = "printcrbitm";
let EncoderMethod = "get_crbitm_encoding";
} }
// Address operands // Address operands
def memri : Operand<iPTR> { def memri : Operand<iPTR> {

20
lib/Target/PowerPC/PPCMCCodeEmitter.cpp
View File

@ -56,12 +56,14 @@ public:
"Invalid kind!"); "Invalid kind!");
return Infos[Kind - FirstTargetFixupKind]; return Infos[Kind - FirstTargetFixupKind];
} }
unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const;
/// getMachineOpValue - Return binary encoding of operand. If the machine /// getMachineOpValue - Return binary encoding of operand. If the machine
/// operand requires relocation, record the relocation and return zero. /// operand requires relocation, record the relocation and return zero.
unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups) const;
// getBinaryCodeForInstr - TableGen'erated function for getting the // getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction. // binary encoding for an instruction.
@ -89,11 +91,23 @@ MCCodeEmitter *llvm::createPPCMCCodeEmitter(const Target &, TargetMachine &TM,
return new PPCMCCodeEmitter(TM, Ctx); return new PPCMCCodeEmitter(TM, Ctx);
} }
unsigned PPCMCCodeEmitter::
get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const {
const MCOperand &MO = MI.getOperand(OpNo);
assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
(MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
return 0x80 >> PPCRegisterInfo::getRegisterNumbering(MO.getReg());
}
unsigned PPCMCCodeEmitter:: unsigned PPCMCCodeEmitter::
getMachineOpValue(const MCInst &MI, const MCOperand &MO, getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups) const {
if (MO.isReg()) if (MO.isReg()) {
assert(MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF);
return PPCRegisterInfo::getRegisterNumbering(MO.getReg()); return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
}
if (MO.isImm()) if (MO.isImm())
return MO.getImm(); return MO.getImm();