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[PowerPC] Clear the sideeffect bit for those instructions that didn't have the match pattern
If the instruction have match pattern, llvm-tblgen will infer the sideeffect bit from the match pattern and it works well. If not, the tblgen will set it as true that hurt the scheduling. PowerPC has some instructions that didn't specify the match pattern(i.e. LXSD etc), which is manually selected post-ra according to the register pressure. We need to clear the sideeffect flag for these instructions. Differential Revision: https://reviews.llvm.org/D69232
This commit is contained in:
QingShan Zhang
parent
0ad4d87942
commit
6f49436f61
@ -943,7 +943,7 @@ def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src),
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[(set i64:$rD, (sextloadi32 xaddrX4:$src))]>, isPPC64,
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PPC970_DGroup_Cracked;
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// For fast-isel:
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let isCodeGenOnly = 1, mayLoad = 1 in {
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let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in {
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def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
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"lwa $rD, $src", IIC_LdStLWA, []>, isPPC64,
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PPC970_DGroup_Cracked;
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@ -2039,6 +2039,7 @@ def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$frD), (ins memrr:$src),
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}
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// Load Multiple
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let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
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def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
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"lmw $rD, $src", IIC_LdStLMW, []>;
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@ -2193,6 +2194,7 @@ def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
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}
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// Store Multiple
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let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
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def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
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"stmw $rS, $dst", IIC_LdStLMW, []>;
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@ -1379,7 +1379,7 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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[(set v4i32:$XT, (or v4i32:$XA, (vnot_ppc v4i32:$XB)))]>;
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// VSX scalar loads introduced in ISA 2.07
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let mayLoad = 1, mayStore = 0 in {
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let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {
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let CodeSize = 3 in
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def LXSSPX : XX1Form_memOp<31, 524, (outs vssrc:$XT), (ins memrr:$src),
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"lxsspx $XT, $src", IIC_LdStLFD, []>;
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@ -1404,7 +1404,7 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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} // mayLoad
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// VSX scalar stores introduced in ISA 2.07
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let mayStore = 1, mayLoad = 0 in {
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let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {
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let CodeSize = 3 in
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def STXSSPX : XX1Form_memOp<31, 652, (outs), (ins vssrc:$XT, memrr:$dst),
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"stxsspx $XT, $dst", IIC_LdStSTFD, []>;
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@ -2977,7 +2977,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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// When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in
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// PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging.
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let mayLoad = 1, mayStore = 0 in {
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let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {
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// Load Vector
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def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins memrix16:$src),
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"lxv $XT, $src", IIC_LdStLFD, []>;
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@ -3022,7 +3022,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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// When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in
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// PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging.
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let mayStore = 1, mayLoad = 0 in {
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let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {
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// Store Vector
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def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, memrix16:$dst),
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"stxv $XT, $dst", IIC_LdStSTFD, []>;
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@ -3769,7 +3769,7 @@ let AddedComplexity = 400 in {
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}
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}
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let Predicates = [HasP9Vector] in {
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let Predicates = [HasP9Vector], hasSideEffects = 0 in {
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let mayStore = 1 in {
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def SPILLTOVSR_STX : PseudoXFormMemOp<(outs),
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(ins spilltovsrrc:$XT, memrr:$dst),
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@ -794,8 +794,6 @@ define void @test_13_consecutive_stores_of_bytes(<16 x i8> %a, i8* nocapture %b)
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;
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; CHECK-P9-LABEL: test_13_consecutive_stores_of_bytes:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: vsldoi v3, v2, v2, 4
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; CHECK-P9-NEXT: stxsibx vs35, 0, r5
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; CHECK-P9-NEXT: vsldoi v3, v2, v2, 12
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; CHECK-P9-NEXT: li r3, 1
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; CHECK-P9-NEXT: stxsibx vs35, r5, r3
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@ -808,6 +806,8 @@ define void @test_13_consecutive_stores_of_bytes(<16 x i8> %a, i8* nocapture %b)
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; CHECK-P9-NEXT: vsldoi v3, v2, v2, 2
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; CHECK-P9-NEXT: li r3, 4
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; CHECK-P9-NEXT: stxsibx vs35, r5, r3
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; CHECK-P9-NEXT: vsldoi v3, v2, v2, 4
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; CHECK-P9-NEXT: stxsibx vs35, 0, r5
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; CHECK-P9-NEXT: vsldoi v3, v2, v2, 8
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; CHECK-P9-NEXT: li r3, 5
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; CHECK-P9-NEXT: stxsibx vs35, r5, r3
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@ -836,19 +836,19 @@ define void @test_13_consecutive_stores_of_bytes(<16 x i8> %a, i8* nocapture %b)
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;
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; CHECK-P9-BE-LABEL: test_13_consecutive_stores_of_bytes:
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; CHECK-P9-BE: # %bb.0: # %entry
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; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 13
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; CHECK-P9-BE-NEXT: stxsibx vs35, 0, r5
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; CHECK-P9-BE-NEXT: li r3, 3
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; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 5
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; CHECK-P9-BE-NEXT: stxsibx vs34, r5, r3
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; CHECK-P9-BE-NEXT: li r3, 1
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; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3
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; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 2
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; CHECK-P9-BE-NEXT: li r3, 2
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; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3
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; CHECK-P9-BE-NEXT: li r3, 3
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; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 15
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; CHECK-P9-BE-NEXT: stxsibx vs34, r5, r3
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; CHECK-P9-BE-NEXT: li r3, 4
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; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3
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; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 13
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; CHECK-P9-BE-NEXT: stxsibx vs35, 0, r5
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; CHECK-P9-BE-NEXT: vsldoi v3, v2, v2, 9
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; CHECK-P9-BE-NEXT: li r3, 5
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; CHECK-P9-BE-NEXT: stxsibx vs35, r5, r3
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@ -1,19 +1,58 @@
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; REQUIRES: asserts
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK-P9
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define i64 @store_disjoint_memory(i64* nocapture %P, i64 %v) {
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entry:
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: store_disjoint_memory:%bb.0
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; CHECK:SU(2): STD renamable $x4, 24, renamable $x5 :: (store 8 into %ir.arrayidx)
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; CHECK:SU([[REG2:[0-9]+]]): STD renamable $x{{[0-9]+}}, 24, renamable $x[[REG5:[0-9]+]]
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; CHECK-NOT: Successors:
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; CHECK-NOT: SU(3): Ord Latency=0 Memory
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; CHECK:SU(3): STD renamable $x4, 16, renamable $x5 :: (store 8 into %ir.arrayidx1)
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; CHECK-NOT: SU([[REG3]]): Ord Latency=0 Memory
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; CHECK:SU([[REG3:[0-9]+]]): STD renamable $x{{[0-9]+}}, 16, renamable $x[[REG5]]
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; CHECK: Predecessors:
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; CHECK-NOT: SU(2): Ord Latency=0 Memory
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; CHECK-NOT: SU([[REG2]]): Ord Latency=0 Memory
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%arrayidx = getelementptr inbounds i64, i64* %P, i64 3
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store i64 %v, i64* %arrayidx
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%arrayidx1 = getelementptr inbounds i64, i64* %P, i64 2
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store i64 %v, i64* %arrayidx1
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ret i64 %v
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}
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; LXSD is an instruction that can be modeled.
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@gd = external local_unnamed_addr global [500 x double], align 8
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@gf = external local_unnamed_addr global [500 x float], align 4
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define double @test_lxsd_no_barrier(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, double %j, double %k, double %l, double %m) {
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entry:
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%0 = load double, double* getelementptr inbounds ([500 x double], [500 x double]* @gd, i64 0, i64 10), align 8
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%1 = load double, double* getelementptr inbounds ([500 x double], [500 x double]* @gd, i64 0, i64 17), align 8
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%2 = load double, double* getelementptr inbounds ([500 x double], [500 x double]* @gd, i64 0, i64 87), align 8
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%3 = load double, double* getelementptr inbounds ([500 x double], [500 x double]* @gd, i64 0, i64 97), align 8
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%4 = load double, double* getelementptr inbounds ([500 x double], [500 x double]* @gd, i64 0, i64 77), align 8
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%add = fadd double %a, %b
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%add1 = fadd double %add, %c
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%add2 = fadd double %add1, %d
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%add3 = fadd double %add2, %e
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%add4 = fadd double %add3, %f
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%add5 = fadd double %add4, %g
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%add6 = fadd double %add5, %h
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%add7 = fadd double %add6, %i
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%add8 = fadd double %add7, %j
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%add9 = fadd double %add8, %k
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%add10 = fadd double %add9, %l
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%add11 = fadd double %add10, %m
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%add12 = fadd double %add11, %0
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%add13 = fadd double %add12, %1
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%add14 = fadd double %add13, %2
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%add15 = fadd double %add14, %3
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%add16 = fadd double %add15, %4
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ret double %add16
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; CHECK-P9: ********** MI Scheduling **********
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; CHECK-P9-LABEL: test_lxsd_no_barrier:%bb.0 entry
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; CHECK-P9-NOT:Global memory object and new barrier chain: SU({{[0-9]+}}).
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; CHECK-P9:SU({{[0-9]+}}): renamable $vf{{[0-9]+}} = LXSD 136
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; CHECK-P9:SU({{[0-9]+}}): renamable $vf{{[0-9]+}} = LXSD 696
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; CHECK-P9:SU({{[0-9]+}}): renamable $vf{{[0-9]+}} = LXSD 776
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; CHECK-P9:SU({{[0-9]+}}): renamable $vf{{[0-9]+}} = LXSD 616
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}
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