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SparcInstr.def: added 'r' and 'i' versions of MOV(F)cc instructions
SparcInstrSelection.cpp: * Fixed opcodes to return correct 'i' version since the two functions are each only used in one place. * Changed name of function to have an 'i' in the name to signify that they each return an immediate form of the opcode. * Added a warning if either of the functions is ever used in a context which requires a register-version opcode. SparcV9_F4.td: fixed class F4_3, added F4_4 and notes that F4_{1,2} need fixing SparcV9.td: added the MOV(F)cc instructions llvm-svn: 6548
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lib/Target/Sparc
@ -244,44 +244,76 @@ I(MOVRGEZ, "movrgez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_
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// Conditional move on integer condition code.
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// The first argument specifies the ICC register: %icc or %xcc
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I(MOVA , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVN , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVNE , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVE , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVG , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVLE , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVGE , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVL , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVGU , "movgu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVLEU, "movleu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVCC , "movcc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVCS , "movcs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVPOS, "movpos", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVNEG, "movneg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVVC , "movvc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVVS , "movvs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVAr , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVAi , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVNr , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVNi , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVNEr , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVNEi , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVEr , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVEi , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVGr , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVGi , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVLEr , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVLEi , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVGEr , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVGEi , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVLr , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVLi , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVGUr , "movgu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVGUi , "movgu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVLEUr, "movleu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVLEUi, "movleu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVCCr , "movcc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVCCi , "movcc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVCSr , "movcs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVCSi , "movcs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVPOSr, "movpos", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVPOSi, "movpos", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVNEGr, "movneg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVNEGi, "movneg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVVCr , "movvc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVVCi , "movvc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVVSr , "movvs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVVSi , "movvs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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// Conditional move (of integer register) on floating point condition code.
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// The first argument is the FCCn register (0 <= n <= 3).
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// Note that the enum name above is not the same as the assembly mnemonic
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// because some of the assembly mnemonics are the same as the move on
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// integer CC (e.g., MOVG), and we cannot have the same enum entry twice.
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I(MOVFA , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFN , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFU , "movu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFG , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFUG , "movug", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFL , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFUL , "movul", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFLG , "movlg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFNE , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFE , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFUE , "movue", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFGE , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFUGE, "movuge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFLE , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFULE, "movule", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFO , "movo", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFAr , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFAi , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFNr , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFNi , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFUr , "movu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFUi , "movu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFGr , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFGi , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFUGr , "movug", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFUGi , "movug", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFLr , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFLi , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFULr , "movul", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFULi , "movul", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFLGr , "movlg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFLGi , "movlg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFNEr , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFNEi , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFEr , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFEi , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFUEr , "movue", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFUEi , "movue", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFGEr , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFGEi , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFUGEr, "movuge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFUGEi, "movuge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFLEr , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFLEi , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFULEr, "movule", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFULEi, "movule", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFOr , "movo", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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I(MOVFOi , "movo", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG)
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// Conditional move of floating point register on each of the above:
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// i. on integer comparison with zero.
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@ -402,19 +402,26 @@ ChooseBccInstruction(const InstructionNode* instrNode,
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}
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// WARNING: since this function has only one caller, it always returns
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// the opcode that expects an immediate and a register. If this function
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// is ever used in cases where an opcode that takes two registers is required,
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// then modify this function and use convertOpcodeFromRegToImm() where required.
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//
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// It will be necessary to expand convertOpcodeFromRegToImm() to handle the
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// new cases of opcodes.
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static inline MachineOpCode
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ChooseMovFpccInstruction(const InstructionNode* instrNode)
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ChooseMovFpcciInstruction(const InstructionNode* instrNode)
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{
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MachineOpCode opCode = V9::INVALID_OPCODE;
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switch(instrNode->getInstruction()->getOpcode())
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{
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case Instruction::SetEQ: opCode = V9::MOVFE; break;
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case Instruction::SetNE: opCode = V9::MOVFNE; break;
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case Instruction::SetLE: opCode = V9::MOVFLE; break;
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case Instruction::SetGE: opCode = V9::MOVFGE; break;
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case Instruction::SetLT: opCode = V9::MOVFL; break;
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case Instruction::SetGT: opCode = V9::MOVFG; break;
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case Instruction::SetEQ: opCode = V9::MOVFEi; break;
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case Instruction::SetNE: opCode = V9::MOVFNEi; break;
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case Instruction::SetLE: opCode = V9::MOVFLEi; break;
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case Instruction::SetGE: opCode = V9::MOVFGEi; break;
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case Instruction::SetLT: opCode = V9::MOVFLi; break;
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case Instruction::SetGT: opCode = V9::MOVFGi; break;
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default:
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assert(0 && "Unrecognized VM instruction!");
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break;
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@ -432,19 +439,26 @@ ChooseMovFpccInstruction(const InstructionNode* instrNode)
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// (i.e., we want to test inverse of a condition)
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// (The latter two cases do not seem to arise because SetNE needs nothing.)
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//
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// WARNING: since this function has only one caller, it always returns
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// the opcode that expects an immediate and a register. If this function
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// is ever used in cases where an opcode that takes two registers is required,
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// then modify this function and use convertOpcodeFromRegToImm() where required.
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//
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// It will be necessary to expand convertOpcodeFromRegToImm() to handle the
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// new cases of opcodes.
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static MachineOpCode
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ChooseMovpccAfterSub(const InstructionNode* instrNode)
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ChooseMovpcciAfterSub(const InstructionNode* instrNode)
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{
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MachineOpCode opCode = V9::INVALID_OPCODE;
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switch(instrNode->getInstruction()->getOpcode())
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{
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case Instruction::SetEQ: opCode = V9::MOVE; break;
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case Instruction::SetLE: opCode = V9::MOVLE; break;
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case Instruction::SetGE: opCode = V9::MOVGE; break;
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case Instruction::SetLT: opCode = V9::MOVL; break;
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case Instruction::SetGT: opCode = V9::MOVG; break;
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case Instruction::SetNE: opCode = V9::MOVNE; break;
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case Instruction::SetEQ: opCode = V9::MOVEi; break;
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case Instruction::SetLE: opCode = V9::MOVLEi; break;
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case Instruction::SetGE: opCode = V9::MOVGEi; break;
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case Instruction::SetLT: opCode = V9::MOVLi; break;
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case Instruction::SetGT: opCode = V9::MOVGi; break;
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case Instruction::SetNE: opCode = V9::MOVNEi; break;
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default: assert(0 && "Unrecognized VM instr!"); break;
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}
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@ -2049,8 +2063,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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if (computeBoolVal) {
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MachineOpCode movOpCode = (isFPCompare
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? ChooseMovFpccInstruction(subtreeRoot)
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: ChooseMovpccAfterSub(subtreeRoot));
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? ChooseMovFpcciInstruction(subtreeRoot)
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: ChooseMovpcciAfterSub(subtreeRoot));
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// Unconditionally set register to 0
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M = BuildMI(V9::SETHI, 2).addZImm(0).addRegDef(setCCInstr);
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@ -381,42 +381,72 @@ def FMOVFO : F4_7<2, 0b110101, 0b1111, "fmovfo">; // fmovfo r, r
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// Section A.35: Move Integer Register on Condition (MOVcc) - p194
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// For integer condition codes
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#if 0
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def MOVA :
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def MOVN :
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def MOVNE :
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def MOVE :
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def MOVG :
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def MOVLE :
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def MOVGE :
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def MOVL :
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def MOVGU :
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def MOVLEU :
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def MOVCC :
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def MOVCS :
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def MOVPOS :
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def MOVNEG :
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def MOVVC :
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def MOVVS :
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def MOVAr : F4_3<2, 0b101100, 0b1000, "mova">; // mova i/xcc, rs2, rd
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def MOVAi : F4_4<2, 0b101100, 0b1000, "mova">; // mova i/xcc, rs2, rd
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def MOVNr : F4_3<2, 0b101100, 0b0000, "movn">; // mova i/xcc, rs2, rd
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def MOVNi : F4_4<2, 0b101100, 0b0000, "movn">; // mova i/xcc, rs2, rd
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def MOVNEr : F4_3<2, 0b101100, 0b1001, "movne">; // mova i/xcc, rs2, rd
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def MOVNEi : F4_4<2, 0b101100, 0b1001, "movne">; // mova i/xcc, rs2, rd
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def MOVEr : F4_3<2, 0b101100, 0b0001, "move">; // mova i/xcc, rs2, rd
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def MOVEi : F4_4<2, 0b101100, 0b0001, "move">; // mova i/xcc, rs2, rd
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def MOVGr : F4_3<2, 0b101100, 0b1010, "movg">; // mova i/xcc, rs2, rd
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def MOVGi : F4_4<2, 0b101100, 0b1010, "movg">; // mova i/xcc, rs2, rd
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def MOVLEr : F4_3<2, 0b101100, 0b0010, "movle">; // mova i/xcc, rs2, rd
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def MOVLEi : F4_4<2, 0b101100, 0b0010, "movle">; // mova i/xcc, rs2, rd
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def MOVGEr : F4_3<2, 0b101100, 0b1011, "movge">; // mova i/xcc, rs2, rd
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def MOVGEi : F4_4<2, 0b101100, 0b1011, "movge">; // mova i/xcc, rs2, rd
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def MOVLr : F4_3<2, 0b101100, 0b0011, "movl">; // mova i/xcc, rs2, rd
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def MOVLi : F4_4<2, 0b101100, 0b0011, "movl">; // mova i/xcc, rs2, rd
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def MOVGUr : F4_3<2, 0b101100, 0b1100, "movgu">; // mova i/xcc, rs2, rd
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def MOVGUi : F4_4<2, 0b101100, 0b1100, "movgu">; // mova i/xcc, rs2, rd
|
||||
def MOVLEUr : F4_3<2, 0b101100, 0b0100, "movleu">; // mova i/xcc, rs2, rd
|
||||
def MOVLEUi : F4_4<2, 0b101100, 0b0100, "movleu">; // mova i/xcc, rs2, rd
|
||||
def MOVCCr : F4_3<2, 0b101100, 0b1101, "movcc">; // mova i/xcc, rs2, rd
|
||||
def MOVCCi : F4_4<2, 0b101100, 0b1101, "movcc">; // mova i/xcc, rs2, rd
|
||||
def MOVCSr : F4_3<2, 0b101100, 0b0101, "movcs">; // mova i/xcc, rs2, rd
|
||||
def MOVCSi : F4_4<2, 0b101100, 0b0101, "movcs">; // mova i/xcc, rs2, rd
|
||||
def MOVPOSr : F4_3<2, 0b101100, 0b1110, "movpos">; // mova i/xcc, rs2, rd
|
||||
def MOVPOSi : F4_4<2, 0b101100, 0b1110, "movpos">; // mova i/xcc, rs2, rd
|
||||
def MOVNEGr : F4_3<2, 0b101100, 0b0110, "movneg">; // mova i/xcc, rs2, rd
|
||||
def MOVNEGi : F4_4<2, 0b101100, 0b0110, "movneg">; // mova i/xcc, rs2, rd
|
||||
def MOVVCr : F4_3<2, 0b101100, 0b1111, "movvc">; // mova i/xcc, rs2, rd
|
||||
def MOVVCi : F4_4<2, 0b101100, 0b1111, "movvc">; // mova i/xcc, rs2, rd
|
||||
def MOVVSr : F4_3<2, 0b101100, 0b0111, "movvs">; // mova i/xcc, rs2, rd
|
||||
def MOVVSi : F4_4<2, 0b101100, 0b0111, "movvs">; // mova i/xcc, rs2, rd
|
||||
|
||||
// For floating-point condition codes
|
||||
def MOVFA :
|
||||
def MOVFN :
|
||||
def MOVFU :
|
||||
def MOVFG :
|
||||
def MOVFUG :
|
||||
def MOVFL :
|
||||
def MOVFUL :
|
||||
def MOVFLG :
|
||||
def MOVFNE :
|
||||
def MOVFE :
|
||||
def MOVFUE :
|
||||
def MOVFGE :
|
||||
def MOVFUGE :
|
||||
def MOVFLE :
|
||||
def MOVFULE :
|
||||
def MOVFO :
|
||||
#endif
|
||||
def MOVFAr : F4_3<2, 0b101100, 0b1000, "movfa">; // mova i/xcc, rs2, rd
|
||||
def MOVFAi : F4_4<2, 0b101100, 0b1000, "movfa">; // mova i/xcc, rs2, rd
|
||||
def MOVFNr : F4_3<2, 0b101100, 0b0000, "movfn">; // mova i/xcc, rs2, rd
|
||||
def MOVFNi : F4_4<2, 0b101100, 0b0000, "movfn">; // mova i/xcc, rs2, rd
|
||||
def MOVFUr : F4_3<2, 0b101100, 0b0111, "movfu">; // mova i/xcc, rs2, rd
|
||||
def MOVFUi : F4_4<2, 0b101100, 0b0111, "movfu">; // mova i/xcc, rs2, rd
|
||||
def MOVFGr : F4_3<2, 0b101100, 0b0110, "movfg">; // mova i/xcc, rs2, rd
|
||||
def MOVFGi : F4_4<2, 0b101100, 0b0110, "movfg">; // mova i/xcc, rs2, rd
|
||||
def MOVFUGr : F4_3<2, 0b101100, 0b0101, "movfug">; // mova i/xcc, rs2, rd
|
||||
def MOVFUGi : F4_4<2, 0b101100, 0b0101, "movfug">; // mova i/xcc, rs2, rd
|
||||
def MOVFLr : F4_3<2, 0b101100, 0b0100, "movfl">; // mova i/xcc, rs2, rd
|
||||
def MOVFLi : F4_4<2, 0b101100, 0b0100, "movfl">; // mova i/xcc, rs2, rd
|
||||
def MOVFULr : F4_3<2, 0b101100, 0b0011, "movful">; // mova i/xcc, rs2, rd
|
||||
def MOVFULi : F4_4<2, 0b101100, 0b0011, "movful">; // mova i/xcc, rs2, rd
|
||||
def MOVFLGr : F4_3<2, 0b101100, 0b0010, "movflg">; // mova i/xcc, rs2, rd
|
||||
def MOVFLGi : F4_4<2, 0b101100, 0b0010, "movflg">; // mova i/xcc, rs2, rd
|
||||
def MOVFNEr : F4_3<2, 0b101100, 0b0001, "movfne">; // mova i/xcc, rs2, rd
|
||||
def MOVFNEi : F4_4<2, 0b101100, 0b0001, "movfne">; // mova i/xcc, rs2, rd
|
||||
def MOVFEr : F4_3<2, 0b101100, 0b1001, "movfe">; // mova i/xcc, rs2, rd
|
||||
def MOVFEi : F4_4<2, 0b101100, 0b1001, "movfe">; // mova i/xcc, rs2, rd
|
||||
def MOVFUEr : F4_3<2, 0b101100, 0b1010, "movfue">; // mova i/xcc, rs2, rd
|
||||
def MOVFUEi : F4_4<2, 0b101100, 0b1010, "movfue">; // mova i/xcc, rs2, rd
|
||||
def MOVFGEr : F4_3<2, 0b101100, 0b1011, "movfge">; // mova i/xcc, rs2, rd
|
||||
def MOVFGEi : F4_4<2, 0b101100, 0b1011, "movfge">; // mova i/xcc, rs2, rd
|
||||
def MOVFUGEr : F4_3<2, 0b101100, 0b1100, "movfuge">; // mova i/xcc, rs2, rd
|
||||
def MOVFUGEi : F4_4<2, 0b101100, 0b1100, "movfuge">; // mova i/xcc, rs2, rd
|
||||
def MOVFLEr : F4_3<2, 0b101100, 0b1101, "movfle">; // mova i/xcc, rs2, rd
|
||||
def MOVFLEi : F4_4<2, 0b101100, 0b1101, "movfle">; // mova i/xcc, rs2, rd
|
||||
def MOVFULEr : F4_3<2, 0b101100, 0b1110, "movfule">; // mova i/xcc, rs2, rd
|
||||
def MOVFULEi : F4_4<2, 0b101100, 0b1110, "movfule">; // mova i/xcc, rs2, rd
|
||||
def MOVFOr : F4_3<2, 0b101100, 0b1111, "movfo">; // mova i/xcc, rs2, rd
|
||||
def MOVFOi : F4_4<2, 0b101100, 0b1111, "movfo">; // mova i/xcc, rs2, rd
|
||||
|
||||
// FIXME: Section A.36: Move Integer Register on Register Condition (MOVR)
|
||||
|
||||
|
@ -53,8 +53,23 @@ class F4_rs1rs2 : F4_rs1 {
|
||||
set Inst{4-0} = rs2;
|
||||
}
|
||||
|
||||
// F4_cc - Common class of instructions that have a cond field
|
||||
class F4_cond : F4 {
|
||||
bits<4> cond;
|
||||
set Inst{17-14} = cond;
|
||||
}
|
||||
|
||||
// F4_cc - Common class of instructions that have cc register as first operand
|
||||
class F4_condcc : F4_cond {
|
||||
bits<3> cc;
|
||||
set Inst{18} = cc{2};
|
||||
set Inst{12} = cc{1};
|
||||
set Inst{11} = cc{0};
|
||||
}
|
||||
|
||||
// Actual F4 instruction classes
|
||||
|
||||
// FIXME: order of operands is incorrect!!
|
||||
class F4_1<bits<2> opVal, bits<6> op3Val, string name> : F4_rdrs1rs2 {
|
||||
bits<2> cc;
|
||||
|
||||
@ -66,6 +81,7 @@ class F4_1<bits<2> opVal, bits<6> op3Val, string name> : F4_rdrs1rs2 {
|
||||
//set Inst{10-5} = dontcare;
|
||||
}
|
||||
|
||||
// FIXME: order of operands is incorrect!!
|
||||
class F4_2<bits<2> opVal, bits<6> op3Val, string name> : F4_rdsimm11rs1 {
|
||||
bits<2> cc;
|
||||
|
||||
@ -76,15 +92,31 @@ class F4_2<bits<2> opVal, bits<6> op3Val, string name> : F4_rdsimm11rs1 {
|
||||
set Inst{12-11} = cc;
|
||||
}
|
||||
|
||||
class F4_3<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
|
||||
class F4_3<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
|
||||
string name> : F4_condcc {
|
||||
bits<5> rs2;
|
||||
bits<2> cc;
|
||||
|
||||
set op = opVal;
|
||||
set op3 = op3Val;
|
||||
set cond = condVal;
|
||||
set Name = name;
|
||||
set Inst{13} = 0; // i bit
|
||||
set Inst{12-11} = cc;
|
||||
//set Inst{10-5} = dontcare;
|
||||
set Inst{4-0} = rs2;
|
||||
}
|
||||
|
||||
class F4_4<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
|
||||
string name> : F4_condcc {
|
||||
bits<11> sim11;
|
||||
bits<5> rd;
|
||||
|
||||
set op = opVal;
|
||||
set op3 = op3Val;
|
||||
set cond = condVal;
|
||||
set Name = name;
|
||||
set Inst{13} = 1; // i bit
|
||||
set Inst{10-0} = sim11;
|
||||
}
|
||||
|
||||
|
||||
// FIXME: F4 classes 4
|
||||
|
Loading…
x
Reference in New Issue
Block a user