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[ms-inline asm] Expose the Kind and Opcode variables from the

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MatchInstructionImpl() function.

These values are used by the ConvertToMCInst() function to index into the
ConversionTable.  The values are also needed to call the GetMCInstOperandNum()
function.

llvm-svn: 163101
This commit is contained in:
Chad Rosier 2012-09-03 02:06:46 +00:00
parent ee2993d684
commit 6fbf85d859
5 changed files with 34 additions and 17 deletions
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2
include/llvm/MC/MCTargetAsmParser.h
View File

@ -85,7 +85,7 @@ public:
/// On failure, the target parser is responsible for emitting a diagnostic
/// explaining the match failure.
virtual bool
MatchInstruction(SMLoc IDLoc,
MatchInstruction(SMLoc IDLoc, unsigned &Kind, unsigned &Opcode,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
SmallVectorImpl<MCInst> &MCInsts,
unsigned &OrigErrorInfo,

5
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -7456,9 +7456,12 @@ MatchAndEmitInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out) {
MCInst Inst;
unsigned Kind;
unsigned Opcode;
unsigned ErrorInfo;
unsigned MatchResult;
MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
MatchResult = MatchInstructionImpl(Operands, Kind, Opcode, Inst, ErrorInfo);
switch (MatchResult) {
default: break;
case Match_Success:

4
lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
View File

@ -317,9 +317,11 @@ MatchAndEmitInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out) {
MCInst Inst;
unsigned Kind;
unsigned Opcode;
unsigned ErrorInfo;
switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) {
switch (MatchInstructionImpl(Operands, Kind, Opcode, Inst, ErrorInfo)) {
default: break;
case Match_Success:
Out.EmitInstruction(Inst);

27
lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -67,7 +67,7 @@ private:
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out);
bool MatchInstruction(SMLoc IDLoc,
bool MatchInstruction(SMLoc IDLoc, unsigned &Kind, unsigned &Opcode,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
SmallVectorImpl<MCInst> &MCInsts,
unsigned &OrigErrorInfo,
@ -1516,9 +1516,13 @@ bool X86AsmParser::
MatchAndEmitInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out) {
SmallVector<MCInst, 2> Insts;
unsigned Kind;
unsigned Opcode;
unsigned ErrorInfo;
bool Error = MatchInstruction(IDLoc, Operands, Insts, ErrorInfo);
SmallVector<MCInst, 2> Insts;
bool Error = MatchInstruction(IDLoc, Kind, Opcode, Operands, Insts,
ErrorInfo);
if (!Error)
for (unsigned i = 0, e = Insts.size(); i != e; ++i)
Out.EmitInstruction(Insts[i]);
@ -1526,7 +1530,7 @@ MatchAndEmitInstruction(SMLoc IDLoc,
}
bool X86AsmParser::
MatchInstruction(SMLoc IDLoc,
MatchInstruction(SMLoc IDLoc, unsigned &Kind, unsigned &Opcode,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
SmallVectorImpl<MCInst> &MCInsts, unsigned &OrigErrorInfo,
bool matchingInlineAsm) {
@ -1568,7 +1572,7 @@ MatchInstruction(SMLoc IDLoc,
MCInst Inst;
// First, try a direct match.
switch (MatchInstructionImpl(Operands, Inst, OrigErrorInfo,
switch (MatchInstructionImpl(Operands, Kind, Opcode, Inst, OrigErrorInfo,
isParsingIntelSyntax())) {
default: break;
case Match_Success:
@ -1616,14 +1620,19 @@ MatchInstruction(SMLoc IDLoc,
Tmp[Base.size()] = Suffixes[0];
unsigned ErrorInfoIgnore;
unsigned Match1, Match2, Match3, Match4;
unsigned tKind, tOpcode;
Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
Match1 = MatchInstructionImpl(Operands, tKind, tOpcode, Inst, ErrorInfoIgnore);
if (Match1 == Match_Success) { Kind = tKind; Opcode = tOpcode; }
Tmp[Base.size()] = Suffixes[1];
Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
Match2 = MatchInstructionImpl(Operands, tKind, tOpcode, Inst, ErrorInfoIgnore);
if (Match2 == Match_Success) { Kind = tKind; Opcode = tOpcode; }
Tmp[Base.size()] = Suffixes[2];
Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
Match3 = MatchInstructionImpl(Operands, tKind, tOpcode, Inst, ErrorInfoIgnore);
if (Match3 == Match_Success) { Kind = tKind; Opcode = tOpcode; }
Tmp[Base.size()] = Suffixes[3];
Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
Match4 = MatchInstructionImpl(Operands, tKind, tOpcode, Inst, ErrorInfoIgnore);
if (Match4 == Match_Success) { Kind = tKind; Opcode = tOpcode; }
// Restore the old token.
Op->setTokenValue(Base);

13
utils/TableGen/AsmMatcherEmitter.cpp
View File

@ -2585,9 +2585,10 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
<< "&Operands,\n unsigned OperandNum, unsigned "
<< "&MCOperandNum);\n";
OS << " bool MnemonicIsValid(StringRef Mnemonic);\n";
OS << " unsigned MatchInstructionImpl(\n";
OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
OS << " MCInst &Inst, unsigned &ErrorInfo, unsigned VariantID = 0);\n";
OS << " unsigned MatchInstructionImpl(\n"
<< " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n"
<< " unsigned &Kind, unsigned &Opcode, MCInst &Inst, "
<< "unsigned &ErrorInfo,\n unsigned VariantID = 0);\n";
if (Info.OperandMatchInfo.size()) {
OS << "\n enum OperandMatchResultTy {\n";
@ -2767,8 +2768,8 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
<< Target.getName() << ClassName << "::\n"
<< "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
<< " &Operands,\n";
OS << " MCInst &Inst, unsigned &ErrorInfo, ";
OS << "unsigned VariantID) {\n";
OS << " unsigned &Kind, unsigned &Opcode, MCInst &Inst,";
OS << "\n unsigned &ErrorInfo, unsigned VariantID) {\n";
OS << " // Eliminate obvious mismatches.\n";
OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
@ -2885,6 +2886,8 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
if (!InsnCleanupFn.empty())
OS << " " << InsnCleanupFn << "(Inst);\n";
OS << " Kind = it->ConvertFn;\n";
OS << " Opcode = it->Opcode;\n";
OS << " return Match_Success;\n";
OS << " }\n\n";