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Don't mark scalar integer multiplication as Expand on x86, since x86

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has plain one-result scalar integer multiplication instructions.
This avoids expanding such instructions into MUL_LOHI sequences that
must be special-cased at isel time, and avoids the problem with that
code that provented memory operands from being folded.

This fixes PR1874, addressesing the most common case. The uncommon
cases of optimizing multiply-high operations will require work
in DAGCombiner.

llvm-svn: 47277
This commit is contained in:
Dan Gohman 2008-02-18 17:55:26 +00:00
parent a378b03483
commit 70b9b2f77f
2 changed files with 14 additions and 5 deletions
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11
lib/Target/X86/X86ISelLowering.cpp
View File

@ -169,35 +169,31 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
}
// Scalar integer multiply, multiply-high, divide, and remainder are
// Scalar integer multiply-high, divide, and remainder are
// lowered to use operations that produce two results, to match the
// available instructions. This exposes the two-result form to trivial
// CSE, which is able to combine x/y and x%y into a single instruction,
// for example. The single-result multiply instructions are introduced
// in X86ISelDAGToDAG.cpp, after CSE, for uses where the the high part
// is not needed.
setOperationAction(ISD::MUL , MVT::i8 , Expand);
setOperationAction(ISD::MULHS , MVT::i8 , Expand);
setOperationAction(ISD::MULHU , MVT::i8 , Expand);
setOperationAction(ISD::SDIV , MVT::i8 , Expand);
setOperationAction(ISD::UDIV , MVT::i8 , Expand);
setOperationAction(ISD::SREM , MVT::i8 , Expand);
setOperationAction(ISD::UREM , MVT::i8 , Expand);
setOperationAction(ISD::MUL , MVT::i16 , Expand);
setOperationAction(ISD::MULHS , MVT::i16 , Expand);
setOperationAction(ISD::MULHU , MVT::i16 , Expand);
setOperationAction(ISD::SDIV , MVT::i16 , Expand);
setOperationAction(ISD::UDIV , MVT::i16 , Expand);
setOperationAction(ISD::SREM , MVT::i16 , Expand);
setOperationAction(ISD::UREM , MVT::i16 , Expand);
setOperationAction(ISD::MUL , MVT::i32 , Expand);
setOperationAction(ISD::MULHS , MVT::i32 , Expand);
setOperationAction(ISD::MULHU , MVT::i32 , Expand);
setOperationAction(ISD::SDIV , MVT::i32 , Expand);
setOperationAction(ISD::UDIV , MVT::i32 , Expand);
setOperationAction(ISD::SREM , MVT::i32 , Expand);
setOperationAction(ISD::UREM , MVT::i32 , Expand);
setOperationAction(ISD::MUL , MVT::i64 , Expand);
setOperationAction(ISD::MULHS , MVT::i64 , Expand);
setOperationAction(ISD::MULHU , MVT::i64 , Expand);
setOperationAction(ISD::SDIV , MVT::i64 , Expand);
@ -205,6 +201,11 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::SREM , MVT::i64 , Expand);
setOperationAction(ISD::UREM , MVT::i64 , Expand);
// 8, 16, and 32-bit plain multiply are legal. And 64-bit multiply
// is also legal on x86-64.
if (!Subtarget->is64Bit())
setOperationAction(ISD::MUL , MVT::i64 , Expand);
setOperationAction(ISD::BR_JT , MVT::Other, Expand);
setOperationAction(ISD::BRCOND , MVT::Other, Custom);
setOperationAction(ISD::BR_CC , MVT::Other, Expand);

8
test/CodeGen/X86/mul-remat.ll Normal file
View File

@ -0,0 +1,8 @@
; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 1
; PR1874
define i32 @test(i32 %a, i32 %b) {
entry:
%tmp3 = mul i32 %b, %a
ret i32 %tmp3
}