RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-12-02 16:36:40 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[mips] Remove CPU-only triples from llvm-objdump commands.

Browse Source 
Summary: They aren't necessary since llvm-objdump can auto-detect the architecture.

Reviewers: sdardis

Subscribers: jfb, dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D20904

llvm-svn: 271653
This commit is contained in:
Daniel Sanders 2016-06-03 10:22:22 +00:00
parent 4070a831c7
commit 70d63fbd2e
7 changed files with 11 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
test/MC/Mips/higher-highest-addressing.s
View File

@ -1,8 +1,8 @@
# RUN: llvm-mc -filetype=obj -triple=mips64el-unknown-linux -mcpu=mips64r2 %s \
# RUN: | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
# RUN: | llvm-objdump -disassemble - | FileCheck %s
# RUN: llvm-mc -filetype=obj -triple=mips64el-unknown-linux -mcpu=mips64r2 %s \
# RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL
# RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL
# Test that R_MIPS_HIGHER and R_MIPS_HIGHEST relocations are created. By using

2
test/MC/Mips/micromips-el-fixup-data.s
View File

@ -1,6 +1,6 @@
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 \
# RUN: -mattr=+micromips 2>&1 -filetype=obj > %t.o
# RUN: llvm-objdump %t.o -triple mipsel -mattr=+micromips -d | FileCheck %s
# RUN: llvm-objdump %t.o -mattr=+micromips -d | FileCheck %s
# Check that fixup data is written in the microMIPS specific little endian
# byte order.

3
test/MC/Mips/mips64extins.ll
View File

@ -1,6 +1,5 @@
; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -target-abi=n64 %s -o - \
; RUN: | llvm-objdump -disassemble -triple mips64el -mattr +mips64r2 - \
; RUN: | FileCheck %s
; RUN: | llvm-objdump -disassemble -mattr +mips64r2 - | FileCheck %s
define i64 @dext(i64 %i) nounwind readnone {
entry:

4
test/MC/Mips/mips64shift.ll
View File

@ -1,8 +1,8 @@
; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -disable-mips-delay-filler %s -o - \
; RUN: | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
; RUN: | llvm-objdump -disassemble - | FileCheck %s
; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - \
; RUN: | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
; RUN: | llvm-objdump -disassemble - | FileCheck %s
define i64 @f3(i64 %a0) nounwind readnone {
entry:

3
test/MC/Mips/nacl-mask.s
View File

@ -1,6 +1,5 @@
# RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-nacl %s \
# RUN: | llvm-objdump -triple mipsel -disassemble -no-show-raw-insn - \
# RUN: | FileCheck %s
# RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
# This test tests that address-masking sandboxing is added when given assembly
# input.

3
test/MC/Mips/sext_64_32.ll
View File

@ -1,4 +1,5 @@
; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | \
; RUN: llvm-objdump -disassemble - | FileCheck %s
; Sign extend from 32 to 64 was creating nonsense opcodes

4
test/Object/Mips/feature.test
View File

@ -1,5 +1,5 @@
RUN: llvm-objdump -disassemble -triple mips64el -mattr +mips64r2 %p/../Inputs/dext-test.elf-mips64r2 \
RUN: | FileCheck %s
RUN: llvm-objdump -disassemble -mattr +mips64r2 %p/../Inputs/dext-test.elf-mips64r2 \
RUN: | FileCheck %s
CHECK: Disassembly of section .text:
CHECK: dext: