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Avoid unecessary opsize byte in segment move to memory

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Segment moves to memory are always 16-bit. Remove invalid 32 and 64
bit variants.

Recommiting with missing clang inline assembly test change.

Fixes PR34478.

Reviewers: rnk, craig.topper

Subscribers: llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D39847

llvm-svn: 318797
This commit is contained in:
Nirav Dave 2017-11-21 19:28:13 +00:00
parent 4812755896
commit 71ae010599
9 changed files with 32 additions and 36 deletions
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10
lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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@ -366,13 +366,15 @@ namespace X86II {
// OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
// OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
// 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
// prefix in 16-bit mode.
// prefix in 16-bit mode. OpSizeIgnore means that the instruction may
// take a optional 0x66 byte but should not emit with one.
OpSizeShift = 7,
OpSizeMask = 0x3 << OpSizeShift,
OpSizeFixed = 0 << OpSizeShift,
OpSize16 = 1 << OpSizeShift,
OpSize32 = 2 << OpSizeShift,
OpSizeFixed = 0 << OpSizeShift,
OpSize16 = 1 << OpSizeShift,
OpSize32 = 2 << OpSizeShift,
OpSizeIgnore = 3 << OpSizeShift,
// AsSize - AdSizeX implies this instruction determines its need of 0x67
// prefix from a normal ModRM memory operand. The other types indicate that

8
lib/Target/X86/X86InstrFormats.td
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@ -157,9 +157,10 @@ def EncEVEX : Encoding<3>;
class OperandSize<bits<2> val> {
bits<2> Value = val;
}
def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix.
def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix.
def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
def OpSizeIgnore : OperandSize<3>; // Takes 0x66 prefix, never emits.
// Address size for encodings that change based on mode.
class AddressSize<bits<2> val> {
@ -174,6 +175,7 @@ def AdSize64 : AddressSize<3>; // Encodes a 64-bit address.
// emitter that various prefix bytes are required.
class OpSize16 { OperandSize OpSize = OpSize16; }
class OpSize32 { OperandSize OpSize = OpSize32; }
class OpSizeIgnore { OperandSize OpSize = OpSizeIgnore; }
class AdSize16 { AddressSize AdSize = AdSize16; }
class AdSize32 { AddressSize AdSize = AdSize32; }
class AdSize64 { AddressSize AdSize = AdSize64; }

4
lib/Target/X86/X86InstrInfo.td
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@ -3165,8 +3165,8 @@ def : InstAlias<"jmpl\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Req
// Force mov without a suffix with a segment and mem to prefer the 'l' form of
// the move. All segment/mem forms are equivalent, this has the shortest
// encoding.
def : InstAlias<"mov\t{$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>;
def : InstAlias<"mov\t{$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>;
def : InstAlias<"mov\t{$mem, $seg|$seg, $mem}", (MOV16sm SEGMENT_REG:$seg, i16mem:$mem), 0>;
def : InstAlias<"mov\t{$seg, $mem|$mem, $seg}", (MOV16ms i16mem:$mem, SEGMENT_REG:$seg), 0>;
// Match 'movq <largeimm>, <reg>' as an alias for movabsq.
def : InstAlias<"mov{q}\t{$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>;

12
lib/Target/X86/X86InstrSystem.td
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@ -175,11 +175,7 @@ def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
let mayStore = 1 in {
def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;
def MOV32ms : I<0x8C, MRMDestMem, (outs), (ins i32mem:$dst, SEGMENT_REG:$src),
"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize32;
def MOV64ms : RI<0x8C, MRMDestMem, (outs), (ins i64mem:$dst, SEGMENT_REG:$src),
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSizeIgnore;
}
def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
@ -189,11 +185,7 @@ def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
let mayLoad = 1 in {
def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16;
def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize32;
def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSizeIgnore;
}
} // SchedRW

2
lib/Target/X86/X86SchedSandyBridge.td
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@ -1550,7 +1550,7 @@ def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> {
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup49], (instregex "JMP(16|32|64)m")>;
def: InstRW<[SBWriteResGroup49], (instregex "MOV64sm")>;
def: InstRW<[SBWriteResGroup49], (instregex "MOV16sm")>;
def SBWriteResGroup50 : SchedWriteRes<[SBPort23,SBPort05]> {
let Latency = 6;

4
test/MC/Disassembler/X86/x86-16.txt
View File

@ -207,7 +207,7 @@
# CHECK: movw %cs, %ax
0x8c 0xc8
# CHECK: movl %cs, (%eax)
# CHECK: movw %cs, (%eax)
0x67 0x66 0x8c 0x08
# CHECK: movw %cs, (%eax)
@ -216,7 +216,7 @@
# CHECK: movl %eax, %cs
0x66 0x8e 0xc8
# CHECK: movl (%eax), %cs
# CHECK: movw (%eax), %cs
0x67 0x66 0x8e 0x08
# CHECK: movw (%eax), %cs

12
test/MC/X86/x86-16.s
View File

@ -248,9 +248,9 @@ cmovnae %bx,%bx
// CHECK: encoding: [0x8c,0xc8]
movw %cs, %ax
// CHECK: movl %cs, (%eax)
// CHECK: encoding: [0x67,0x66,0x8c,0x08]
movl %cs, (%eax)
// CHECK: movw %cs, (%eax)
// CHECK: encoding: [0x67,0x8c,0x08]
mov %cs, (%eax)
// CHECK: movw %cs, (%eax)
// CHECK: encoding: [0x67,0x8c,0x08]
@ -272,9 +272,9 @@ cmovnae %bx,%bx
// CHECK: encoding: [0x8e,0xc8]
mov %ax, %cs
// CHECK: movl (%eax), %cs
// CHECK: encoding: [0x67,0x66,0x8e,0x08]
movl (%eax), %cs
// CHECK: movw (%eax), %cs
// CHECK: encoding: [0x67,0x8e,0x08]
mov (%eax), %cs
// CHECK: movw (%eax), %cs
// CHECK: encoding: [0x67,0x8e,0x08]

12
test/MC/X86/x86-32.s
View File

@ -355,12 +355,12 @@ cmovnae %bx,%bx
// CHECK: encoding: [0x66,0x8c,0xc8]
movw %cs, %ax
// CHECK: movl %cs, (%eax)
// CHECK: movw %cs, (%eax)
// CHECK: encoding: [0x8c,0x08]
movl %cs, (%eax)
mov %cs, (%eax)
// CHECK: movw %cs, (%eax)
// CHECK: encoding: [0x66,0x8c,0x08]
// CHECK: encoding: [0x8c,0x08]
movw %cs, (%eax)
// CHECK: movl %eax, %cs
@ -379,12 +379,12 @@ cmovnae %bx,%bx
// CHECK: encoding: [0x8e,0xc8]
mov %ax, %cs
// CHECK: movl (%eax), %cs
// CHECK: movw (%eax), %cs
// CHECK: encoding: [0x8e,0x08]
movl (%eax), %cs
mov (%eax), %cs
// CHECK: movw (%eax), %cs
// CHECK: encoding: [0x66,0x8e,0x08]
// CHECK: encoding: [0x8e,0x08]
movw (%eax), %cs
// radr://8033374

4
test/MC/X86/x86-64.s
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@ -1082,8 +1082,8 @@ decl %eax // CHECK: decl %eax # encoding: [0xff,0xc8]
// rdar://8208615
mov (%rsi), %gs // CHECK: movl (%rsi), %gs # encoding: [0x8e,0x2e]
mov %gs, (%rsi) // CHECK: movl %gs, (%rsi) # encoding: [0x8c,0x2e]
mov (%rsi), %gs // CHECK: movw (%rsi), %gs # encoding: [0x8e,0x2e]
mov %gs, (%rsi) // CHECK: movw %gs, (%rsi) # encoding: [0x8c,0x2e]
// rdar://8431864