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Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match v4i64 and v8i32.

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llvm-svn: 148106
This commit is contained in:
Craig Topper 2012-01-13 06:59:47 +00:00
parent 85c44d1485
commit 71ea42cc29
2 changed files with 9 additions and 1 deletions
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8
lib/Target/X86/X86InstrSSE.td
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@ -289,6 +289,14 @@ def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
// AVX has no support for 256-bit integer instructions, but since the 128-bit
// VPXOR instruction writes zero to its upper part, it's safe build zeros.
def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
(SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
(SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
(SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;

2
test/CodeGen/X86/avx2-shift.ll
View File

@ -231,7 +231,7 @@ define <32 x i8> @sra_v32i8_7(<32 x i8> %A) nounwind {
%B = ashr <32 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
ret <32 x i8> %B
; CHECK: sra_v32i8_7:
; CHECK: vxorps
; CHECK: vpxor
; CHECK: vpcmpgtb
; CHECK: ret
}