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Add a scheduling model (with itinerary) for the PPC POWER7

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This adds a scheduling model for the POWER7 (P7) core, and enables the
machine-instruction scheduler when targeting the P7. Scheduling for the P7,
like earlier ooo PPC cores, requires considering both dispatch group hazards,
and functional unit resources and latencies. These are both modeled in a
combined itinerary. Dispatch group formation is still handled by the post-RA
scheduler (which still needs to be updated for the P7, but nevertheless does a
pretty good job).

One interesting aspect of this change is that I've also enabled to use of AA
duing CodeGen for the P7 (just as it is for the embedded cores). The benchmark
results seem to support this decision (see below), and while this is normally
useful for in-order cores, and not for ooo cores like the P7, I think that the
dispatch slot hazards are enough like in-order resources to make the AA useful.

Test suite significant performance differences (where negative is a speedup,
and positive is a regression) vs. the current situation:

MultiSource/Benchmarks/BitBench/drop3/drop3
  with AA: N/A
  without AA: -28.7614% +/- 19.8356%
(significantly against AA)

MultiSource/Benchmarks/FreeBench/neural/neural
  with AA: -17.7406% +/- 11.2712%
  without AA: N/A
(significantly in favor of AA)

MultiSource/Benchmarks/SciMark2-C/scimark2
  with AA: -11.2079% +/- 1.80543%
  without AA: -11.3263% +/- 2.79651%

MultiSource/Benchmarks/TSVC/Symbolics-flt/Symbolics-flt
  with AA: -41.8649% +/- 17.0053%
  without AA: -34.5256% +/- 23.7072%

MultiSource/Benchmarks/mafft/pairlocalalign
  with AA: 25.3016% +/- 17.8614%
  without AA: 38.6629% +/- 14.9391%
(significantly in favor of AA)

MultiSource/Benchmarks/sim/sim
  with AA: N/A
  without AA: 13.4844% +/- 7.18195%
(significantly in favor of AA)

SingleSource/Benchmarks/BenchmarkGame/Large/fasta
  with AA: 15.0664% +/- 6.70216%
  without AA: 12.7747% +/- 8.43043%

SingleSource/Benchmarks/BenchmarkGame/puzzle
  with AA: 82.2713% +/- 26.3567%
  without AA: 75.7525% +/- 41.1842%

SingleSource/Benchmarks/Misc/flops-2
  with AA: -37.1621% +/- 20.7964%
  without AA: -35.2342% +/- 20.2999%
(significantly in favor of AA)

These are 99.5% confidence intervals from 5 runs per configuration. Regarding
the choice to turn on AA during CodeGen, of these results, four seem
significantly in favor of using AA, and one seems significantly against. I'm
not making this decision based on these numbers alone, but these results
seem consistent with results I have from other tests, and so I think that, on
balance, using AA is a win.

llvm-svn: 195981
This commit is contained in:
Hal Finkel 2013-11-30 20:55:12 +00:00
parent fa2b249f38
commit 725757ccc8
4 changed files with 390 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/PowerPC/PPC.td
View File

@ -254,7 +254,7 @@ def : ProcessorModel<"pwr6x", G5Model,
FeatureSTFIWX, FeatureLFIWAX,
FeatureFPRND, Feature64Bit,
DeprecatedMFTB, DeprecatedDST]>;
def : ProcessorModel<"pwr7", G5Model,
def : ProcessorModel<"pwr7", P7Model,
[DirectivePwr7, FeatureAltivec,
FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,

1
lib/Target/PowerPC/PPCSchedule.td
View File

@ -117,6 +117,7 @@ include "PPCSchedule440.td"
include "PPCScheduleG4.td"
include "PPCScheduleG4Plus.td"
include "PPCScheduleG5.td"
include "PPCScheduleP7.td"
include "PPCScheduleA2.td"
include "PPCScheduleE500mc.td"
include "PPCScheduleE5500.td"

386
lib/Target/PowerPC/PPCScheduleP7.td Normal file
View File

@ -0,0 +1,386 @@
//===-- PPCScheduleP7.td - PPC P7 Scheduling Definitions ---*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the itinerary class data for the POWER7 processor.
//
//===----------------------------------------------------------------------===//
// Primary reference:
// IBM POWER7 multicore server processor
// B. Sinharoy, et al.
// IBM J. Res. & Dev. (55) 3. May/June 2011.
// Scheduling for the P7 involves tracking two types of resources:
// 1. The dispatch bundle slots
// 2. The functional unit resources
// Dispatch units:
def P7_DU1 : FuncUnit;
def P7_DU2 : FuncUnit;
def P7_DU3 : FuncUnit;
def P7_DU4 : FuncUnit;
def P7_DU5 : FuncUnit;
def P7_DU6 : FuncUnit;
def P7_LS1 : FuncUnit; // Load/Store pipeline 1
def P7_LS2 : FuncUnit; // Load/Store pipeline 2
def P7_FX1 : FuncUnit; // FX pipeline 1
def P7_FX2 : FuncUnit; // FX pipeline 2
// VS pipeline 1 (vector integer ops. always here)
def P7_VS1 : FuncUnit; // VS pipeline 1
// VS pipeline 2 (128-bit stores and perms. here)
def P7_VS2 : FuncUnit; // VS pipeline 2
def P7_CRU : FuncUnit; // CR unit (CR logicals and move-from-SPRs)
def P7_BRU : FuncUnit; // BR unit
// Notes:
// Each LSU pipeline can also execute FX add and logical instructions.
// Each LSU pipeline can complete a load or store in one cycle.
//
// Each store is broken into two parts, AGEN goes to the LSU while a
// "data steering" op. goes to the FXU or VSU.
//
// FX loads have a two cycle load-to-use latency (so one "bubble" cycle).
// VSU loads have a three cycle load-to-use latency (so two "bubble" cycle).
//
// Frequent FX ops. take only one cycle and results can be used again in the
// next cycle (there is a self-bypass). Getting results from the other FX
// pipeline takes an additional cycle.
//
// The VSU XS is similar to the POWER6, but with a pipeline length of 2 cycles
// (instead of 3 cycles on the POWER6). VSU XS handles vector FX-style ops.
// Dispatch of an instruction to VS1 that uses four single prec. inputs
// (either to a float or XC op). prevents dispatch in that cycle to VS2 of any
// floating point instruction.
//
// The VSU PM is similar to the POWER6, but with a pipeline length of 3 cycles
// (instead of 4 cycles on the POWER6). vsel is handled by the PM pipeline
// (unlike on the POWER6).
//
// FMA from the VSUs can forward results in 6 cycles. VS1 XS and vector FP
// share the same write-back, and have a 5-cycle latency difference, so the
// IFU/IDU will not dispatch an XS instructon 5 cycles after a vector FP
// op. has been dispatched to VS1.
//
// Three cycles after an L1 cache hit, a dependent VSU instruction can issue.
//
// Instruction dispatch groups have (at most) four non-branch instructions, and
// two branches. Unlike on the POWER4/5, a branch does not automatically
// end the dispatch group, but a second branch must be the last in the group.
def P7Itineraries : ProcessorItineraries<
[P7_DU1, P7_DU2, P7_DU3, P7_DU4, P7_DU5, P7_DU6,
P7_LS1, P7_LS2, P7_FX1, P7_FX2, P7_VS1, P7_VS2, P7_CRU, P7_BRU], [], [
InstrItinData<IIC_IntSimple , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2,
P7_LS1, P7_LS2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntGeneral , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntCompare , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntDivW , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<36, [P7_FX1, P7_FX2]>],
[36, 1, 1]>,
InstrItinData<IIC_IntDivD , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<68, [P7_FX1, P7_FX2]>],
[68, 1, 1]>,
InstrItinData<IIC_IntMulHW , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[4, 1, 1]>,
InstrItinData<IIC_IntMulHWU , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[4, 1, 1]>,
InstrItinData<IIC_IntMulLI , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[4, 1, 1]>,
InstrItinData<IIC_IntRotate , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntRotateD , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntShift , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntTrapW , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[1, 1]>,
InstrItinData<IIC_IntTrapD , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[1, 1]>,
InstrItinData<IIC_BrB , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
InstrStage<1, [P7_BRU]>],
[3, 1, 1]>,
InstrItinData<IIC_BrCR , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
InstrStage<1, [P7_BRU]>],
[3, 1, 1]>,
InstrItinData<IIC_BrMCR , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
InstrStage<1, [P7_BRU]>],
[3, 1, 1]>,
InstrItinData<IIC_BrMCRX , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
InstrStage<1, [P7_BRU]>],
[3, 1, 1]>,
InstrItinData<IIC_LdStLoad , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_LS1, P7_LS2]>],
[2, 1, 1]>,
InstrItinData<IIC_LdStLoadUpd , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_LS1, P7_LS2], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[2, 2, 1, 1]>,
InstrItinData<IIC_LdStLoadUpdX, [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_DU3], 0>,
InstrStage<1, [P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>,
InstrStage<1, [P7_LS1, P7_LS2], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[3, 3, 1, 1]>,
InstrItinData<IIC_LdStLD , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_LS1, P7_LS2]>],
[2, 1, 1]>,
InstrItinData<IIC_LdStLDU , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_LS1, P7_LS2], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[2, 2, 1, 1]>,
InstrItinData<IIC_LdStLDUX , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_DU3], 0>,
InstrStage<1, [P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>,
InstrStage<1, [P7_LS1, P7_LS2], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[3, 3, 1, 1]>,
InstrItinData<IIC_LdStLFD , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_LS1, P7_LS2]>],
[3, 1, 1]>,
InstrItinData<IIC_LdStLVecX , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_LS1, P7_LS2]>],
[3, 1, 1]>,
InstrItinData<IIC_LdStLFDU , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_LS1, P7_LS2], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[3, 3, 1, 1]>,
InstrItinData<IIC_LdStLFDUX , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_LS1, P7_LS2], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[3, 3, 1, 1]>,
InstrItinData<IIC_LdStLHA , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_LS1, P7_LS2]>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[3, 1, 1]>,
InstrItinData<IIC_LdStLHAU , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_LS1, P7_LS2], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[4, 4, 1, 1]>,
InstrItinData<IIC_LdStLHAUX , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_DU3], 0>,
InstrStage<1, [P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>,
InstrStage<1, [P7_LS1, P7_LS2], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[4, 4, 1, 1]>,
InstrItinData<IIC_LdStLWA , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_LS1, P7_LS2]>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[3, 1, 1]>,
InstrItinData<IIC_LdStLWARX, [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_DU3], 0>,
InstrStage<1, [P7_DU4], 0>,
InstrStage<1, [P7_LS1, P7_LS2]>],
[3, 1, 1]>,
InstrItinData<IIC_LdStLDARX, [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_DU3], 0>,
InstrStage<1, [P7_DU4], 0>,
InstrStage<1, [P7_LS1, P7_LS2]>],
[3, 1, 1]>,
InstrItinData<IIC_LdStLMW , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_LS1, P7_LS2]>],
[2, 1, 1]>,
InstrItinData<IIC_LdStStore , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_LS1, P7_LS2], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[1, 1, 1]>,
InstrItinData<IIC_LdStSTD , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_LS1, P7_LS2], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[1, 1, 1]>,
InstrItinData<IIC_LdStSTDU , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_LS1, P7_LS2], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[2, 1, 1, 1]>,
InstrItinData<IIC_LdStSTDUX , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_DU3], 0>,
InstrStage<1, [P7_DU4], 0>,
InstrStage<1, [P7_LS1, P7_LS2], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[2, 1, 1, 1]>,
InstrItinData<IIC_LdStSTFD , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_LS1, P7_LS2], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>],
[1, 1, 1]>,
InstrItinData<IIC_LdStSTFDU , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_LS1, P7_LS2], 0>,
InstrStage<1, [P7_FX1, P7_FX2], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>],
[2, 1, 1, 1]>,
InstrItinData<IIC_LdStSTVEBX , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_LS1, P7_LS2], 0>,
InstrStage<1, [P7_VS2]>],
[1, 1, 1]>,
InstrItinData<IIC_LdStSTDCX , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_DU3], 0>,
InstrStage<1, [P7_DU4], 0>,
InstrStage<1, [P7_LS1, P7_LS2]>],
[1, 1, 1]>,
InstrItinData<IIC_LdStSTWCX , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_DU2], 0>,
InstrStage<1, [P7_DU3], 0>,
InstrStage<1, [P7_DU4], 0>,
InstrStage<1, [P7_LS1, P7_LS2]>],
[1, 1, 1]>,
InstrItinData<IIC_BrMCRX , [InstrStage<1, [P7_DU4], 0>,
InstrStage<1, [P7_CRU]>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[3, 1]>, // mtcr
InstrItinData<IIC_SprMFCR , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_CRU]>],
[6, 1]>,
InstrItinData<IIC_SprMFCRF , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_CRU]>],
[3, 1]>,
InstrItinData<IIC_FPGeneral , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>],
[5, 1, 1]>,
InstrItinData<IIC_FPCompare , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>],
[8, 1, 1]>,
InstrItinData<IIC_FPDivD , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>],
[33, 1, 1]>,
InstrItinData<IIC_FPDivS , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>],
[27, 1, 1]>,
InstrItinData<IIC_FPSqrtD , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>],
[44, 1, 1]>,
InstrItinData<IIC_FPSqrtS , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>],
[32, 1, 1]>,
InstrItinData<IIC_FPFused , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>],
[5, 1, 1, 1]>,
InstrItinData<IIC_FPRes , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>],
[5, 1, 1]>,
InstrItinData<IIC_VecGeneral , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1]>],
[2, 1, 1]>,
InstrItinData<IIC_VecVSL , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1]>],
[2, 1, 1]>,
InstrItinData<IIC_VecVSR , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1]>],
[2, 1, 1]>,
InstrItinData<IIC_VecFP , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>],
[6, 1, 1]>,
InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>],
[6, 1, 1]>,
InstrItinData<IIC_VecFPRound , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>],
[6, 1, 1]>,
InstrItinData<IIC_VecComplex , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1]>],
[7, 1, 1]>,
InstrItinData<IIC_VecPerm , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS2]>],
[2, 1, 1]>
]>;
// ===---------------------------------------------------------------------===//
// P7 machine model for scheduling and other instruction cost heuristics.
def P7Model : SchedMachineModel {
let IssueWidth = 6; // 4 (non-branch) instructions are dispatched per cycle.
// Note that the dispatch bundle size is 6 (including
// branches), but the total internal issue bandwidth per
// cycle (from all queues) is 8.
let MinLatency = 0; // Out-of-order dispatch.
let LoadLatency = 3; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
let MispredictPenalty = 16;
let Itineraries = P7Itineraries;
}

3
lib/Target/PowerPC/PPCSubtarget.cpp
View File

@ -179,7 +179,7 @@ bool PPCSubtarget::enablePostRAScheduler(
return OptLevel >= CodeGenOpt::Default;
}
// Embedded cores need aggressive scheduling.
// Embedded cores need aggressive scheduling (and some others also benefit).
static bool needsAggressiveScheduling(unsigned Directive) {
switch (Directive) {
default: return false;
@ -187,6 +187,7 @@ static bool needsAggressiveScheduling(unsigned Directive) {
case PPC::DIR_A2:
case PPC::DIR_E500mc:
case PPC::DIR_E5500:
case PPC::DIR_PWR7:
return true;
}
}