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- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT
also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. llvm-svn: 128832
This commit is contained in:
Bruno Cardoso Lopes
parent
94fc1341f5
commit
74363376e4
@ -409,7 +409,7 @@ namespace ARM_AM {
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// The first operand is always a Reg. The second operand is a reg if in
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// reg/reg form, otherwise it's reg#0. The third field encodes the operation
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// in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The
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// forth operand 16-17 encodes the index mode.
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// fourth operand 16-17 encodes the index mode.
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//
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// If this addressing mode is a frame index (before prolog/epilog insertion
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// and code rewriting), this operand will have the form: FI#, reg0, <offs>
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@ -446,12 +446,14 @@ namespace ARM_AM {
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//
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// The first operand is always a Reg. The second operand is a reg if in
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// reg/reg form, otherwise it's reg#0. The third field encodes the operation
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// in bit 8, the immediate in bits 0-7.
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// in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the
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// index mode.
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/// getAM3Opc - This function encodes the addrmode3 opc field.
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static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset) {
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static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset,
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unsigned IdxMode = 0) {
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bool isSub = Opc == sub;
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return ((int)isSub << 8) | Offset;
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return ((int)isSub << 8) | Offset | (IdxMode << 9);
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}
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static inline unsigned char getAM3Offset(unsigned AM3Opc) {
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return AM3Opc & 0xFF;
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@ -459,6 +461,9 @@ namespace ARM_AM {
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static inline AddrOpc getAM3Op(unsigned AM3Opc) {
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return ((AM3Opc >> 8) & 1) ? sub : add;
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}
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static inline unsigned getAM3IdxMode(unsigned AM3Opc) {
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return (AM3Opc >> 9);
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}
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//===--------------------------------------------------------------------===//
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// Addressing Mode #4
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@ -577,6 +577,34 @@ class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
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let Inst{15-12} = Rt; // Rt
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let Inst{7-4} = op;
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}
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// FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
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// but for now use this class for LDRSBT, LDRHT, LDSHT.
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class AI3ldstidxT<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
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IndexMode im, Format f, InstrItinClass itin, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<oops, iops, AddrMode3, Size4Bytes, im, f, itin,
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opc, asm, cstr, pattern> {
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// {13} 1 == imm8, 0 == Rm
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// {12-9} Rn
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// {8} isAdd
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// {7-4} imm7_4/zero
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// {3-0} imm3_0/Rm
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bits<14> addr;
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bits<4> Rt;
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let Inst{27-25} = 0b000;
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let Inst{24} = isPre; // P bit
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let Inst{23} = addr{8}; // U bit
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let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
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let Inst{20} = op20; // L bit
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let Inst{19-16} = addr{12-9}; // Rn
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let Inst{15-12} = Rt; // Rt
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let Inst{11-8} = addr{7-4}; // imm7_4/zero
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let Inst{7-4} = op;
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let Inst{3-0} = addr{3-0}; // imm3_0/Rm
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let AsmMatchConverter = "CvtLdWriteBackRegAddrMode3";
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}
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class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops,
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IndexMode im, Format f, InstrItinClass itin, string opc,
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string asm, string cstr, list<dag> pattern>
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@ -649,12 +677,25 @@ class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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: I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
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opc, asm, cstr,pattern> {
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// {13} 1 == imm8, 0 == Rm
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// {12-9} Rn
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// {8} isAdd
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// {7-4} imm7_4/zero
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// {3-0} imm3_0/Rm
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bits<14> addr;
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bits<4> Rt;
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let Inst{3-0} = addr{3-0}; // imm3_0/Rm
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let Inst{4} = 1;
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let Inst{5} = 1; // H bit
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let Inst{6} = 0; // S bit
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let Inst{7} = 1;
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let Inst{11-8} = addr{7-4}; // imm7_4/zero
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let Inst{15-12} = Rt; // Rt
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let Inst{19-16} = addr{12-9}; // Rn
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let Inst{20} = 0; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
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let Inst{23} = addr{8}; // U bit
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let Inst{24} = 0; // P bit
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let Inst{27-25} = 0b000;
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}
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@ -475,6 +475,17 @@ def width_imm : Operand<i32>, PatLeaf<(imm), [{
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// Define ARM specific addressing modes.
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def MemMode2AsmOperand : AsmOperandClass {
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let Name = "MemMode2";
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let SuperClasses = [];
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let ParserMethod = "tryParseMemMode2Operand";
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}
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def MemMode3AsmOperand : AsmOperandClass {
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let Name = "MemMode3";
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let SuperClasses = [];
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let ParserMethod = "tryParseMemMode3Operand";
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}
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// addrmode_imm12 := reg +/- imm12
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//
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@ -498,12 +509,6 @@ def ldst_so_reg : Operand<i32>,
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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}
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def MemMode2AsmOperand : AsmOperandClass {
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let Name = "MemMode2";
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let SuperClasses = [];
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let ParserMethod = "tryParseMemMode2Operand";
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}
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// addrmode2 := reg +/- imm12
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// := reg +/- reg shop imm
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//
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@ -530,6 +535,7 @@ def addrmode3 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectAddrMode3", []> {
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let EncoderMethod = "getAddrMode3OpValue";
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let PrintMethod = "printAddrMode3Operand";
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let ParserMatchClass = MemMode3AsmOperand;
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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}
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@ -1763,22 +1769,19 @@ def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
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let Inst{11-0} = addr{11-0};
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let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
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}
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def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
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(ins GPR:$base, am3offset:$offset), IndexModePost,
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LdMiscFrm, IIC_iLoad_bh_ru,
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"ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
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def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
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(ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
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"ldrsbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
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let Inst{21} = 1; // overwrite
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}
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def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
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(ins GPR:$base, am3offset:$offset), IndexModePost,
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LdMiscFrm, IIC_iLoad_bh_ru,
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"ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
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def LDRHT : AI3ldstidxT<0b1011, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
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(ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
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"ldrht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
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let Inst{21} = 1; // overwrite
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}
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def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
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(ins GPR:$base, am3offset:$offset), IndexModePost,
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LdMiscFrm, IIC_iLoad_bh_ru,
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"ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
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def LDRSHT : AI3ldstidxT<0b1111, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
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(ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
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"ldrsht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
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let Inst{21} = 1; // overwrite
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}
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}
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@ -1870,12 +1873,12 @@ def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
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let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
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}
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def STRHT: AI3sthpo<(outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am3offset:$offset),
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def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
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StMiscFrm, IIC_iStore_bh_ru,
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"strht", "\t$src, [$base], $offset", "$base = $base_wb",
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"strht", "\t$Rt, $addr", "$addr.base = $base_wb",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{21} = 1; // overwrite
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let AsmMatchConverter = "CvtStWriteBackRegAddrMode3";
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}
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//===----------------------------------------------------------------------===//
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@ -98,12 +98,18 @@ class ARMAsmParser : public TargetAsmParser {
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SmallVectorImpl<MCParsedAsmOperand*>&);
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OperandMatchResultTy tryParseMemMode2Operand(
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SmallVectorImpl<MCParsedAsmOperand*>&);
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OperandMatchResultTy tryParseMemMode3Operand(
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SmallVectorImpl<MCParsedAsmOperand*>&);
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// Asm Match Converter Methods
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bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &);
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bool CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &);
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bool CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &);
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bool CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &);
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public:
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ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
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@ -371,6 +377,30 @@ public:
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return true;
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}
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bool isMemMode3() const {
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if (getMemAddrMode() != ARMII::AddrMode3)
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return false;
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if (getMemOffsetIsReg()) {
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if (getMemOffsetRegShifted())
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return false; // No shift with offset reg allowed
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return true;
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}
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if (getMemNegative() &&
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!(getMemPostindexed() || getMemPreindexed()))
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
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if (!CE) return false;
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int64_t Value = CE->getValue();
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// The offset must be in the range 0-255 (imm8).
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if (Value > 255 || Value < -255)
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return false;
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return true;
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}
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bool isMemMode5() const {
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if (!isMemory() || getMemOffsetIsReg() || getMemWriteback() ||
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getMemNegative())
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@ -539,6 +569,37 @@ public:
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-Offset, ARM_AM::no_shift, IdxMode)));
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}
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void addMemMode3Operands(MCInst &Inst, unsigned N) const {
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assert(isMemMode3() && "Invalid mode or number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
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unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1);
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if (getMemOffsetIsReg()) {
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Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
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ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
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Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(AMOpc, 0,
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IdxMode)));
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return;
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}
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// Create a operand placeholder to always yield the same number of operands.
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Inst.addOperand(MCOperand::CreateReg(0));
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// FIXME: #-0 is encoded differently than #0. Does the parser preserve
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// the difference?
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
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assert(CE && "Non-constant mode 3 offset operand!");
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int64_t Offset = CE->getValue();
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if (Offset >= 0)
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Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::add,
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Offset, IdxMode)));
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else
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Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::sub,
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-Offset, IdxMode)));
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}
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void addMemMode5Operands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && isMemMode5() && "Invalid number of operands!");
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@ -1219,6 +1280,17 @@ tryParseMemMode2Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return MatchOperand_Success;
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}
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/// tryParseMemMode3Operand - Try to parse memory addressing mode 3 operand.
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ARMAsmParser::OperandMatchResultTy ARMAsmParser::
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tryParseMemMode3Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
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if (ParseMemory(Operands, ARMII::AddrMode3))
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return MatchOperand_NoMatch;
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return MatchOperand_Success;
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}
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/// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
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/// Needed here because the Asm Gen Matcher can't handle properly tied operands
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/// when they refer multiple MIOperands inside a single one.
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@ -1249,6 +1321,36 @@ CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
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return true;
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}
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/// CvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
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/// Needed here because the Asm Gen Matcher can't handle properly tied operands
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/// when they refer multiple MIOperands inside a single one.
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bool ARMAsmParser::
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CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
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// Create a writeback register dummy placeholder.
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Inst.addOperand(MCOperand::CreateImm(0));
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((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
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((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
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return true;
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}
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/// CvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
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/// Needed here because the Asm Gen Matcher can't handle properly tied operands
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/// when they refer multiple MIOperands inside a single one.
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bool ARMAsmParser::
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CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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// Create a writeback register dummy placeholder.
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Inst.addOperand(MCOperand::CreateImm(0));
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((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
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((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
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((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
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return true;
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}
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/// Parse an ARM memory expression, return false if successful else return true
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/// or an error. The first token must be a '[' when called.
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///
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@ -1310,6 +1412,10 @@ ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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const AsmToken &ExclaimTok = Parser.getTok();
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if (ExclaimTok.is(AsmToken::Exclaim)) {
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// None of addrmode3 instruction uses "!"
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if (AddrMode == ARMII::AddrMode3)
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return true;
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WBOp = ARMOperand::CreateToken(ExclaimTok.getString(),
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ExclaimTok.getLoc());
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Writeback = true;
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@ -1350,6 +1456,11 @@ ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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if (!OffsetIsReg) {
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if (!Offset)
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Offset = MCConstantExpr::Create(0, getContext());
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} else {
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if (AddrMode == ARMII::AddrMode3 && OffsetRegShifted) {
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Error(E, "shift amount not supported");
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return true;
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}
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}
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Operands.push_back(ARMOperand::CreateMem(AddrMode, BaseRegNum, OffsetIsReg,
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@ -1237,19 +1237,22 @@ static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
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"Expect 1 reg operand followed by 1 imm operand");
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ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
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unsigned IndexMode =
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(TID.TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
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if (getAM3IBit(insn) == 1) {
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MI.addOperand(MCOperand::CreateReg(0));
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// Disassemble the 8-bit immediate offset.
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unsigned Imm4H = (insn >> ARMII::ImmHiShift) & 0xF;
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unsigned Imm4L = insn & 0xF;
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unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, (Imm4H << 4) | Imm4L);
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unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, (Imm4H << 4) | Imm4L,
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IndexMode);
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MI.addOperand(MCOperand::CreateImm(Offset));
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} else {
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// Disassemble the offset reg (Rm).
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
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decodeRm(insn))));
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unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0);
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unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0, IndexMode);
|
||||
MI.addOperand(MCOperand::CreateImm(Offset));
|
||||
}
|
||||
OpIdx += 2;
|
||||
|
||||
@ -181,6 +181,10 @@ void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
|
||||
}
|
||||
}
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// Addressing Mode #2
|
||||
//===--------------------------------------------------------------------===//
|
||||
|
||||
void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
|
||||
raw_ostream &O) {
|
||||
const MCOperand &MO1 = MI->getOperand(Op);
|
||||
@ -276,11 +280,35 @@ void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
|
||||
<< " #" << ShImm;
|
||||
}
|
||||
|
||||
void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
const MCOperand &MO1 = MI->getOperand(OpNum);
|
||||
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
||||
const MCOperand &MO3 = MI->getOperand(OpNum+2);
|
||||
//===--------------------------------------------------------------------===//
|
||||
// Addressing Mode #3
|
||||
//===--------------------------------------------------------------------===//
|
||||
|
||||
void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
|
||||
raw_ostream &O) {
|
||||
const MCOperand &MO1 = MI->getOperand(Op);
|
||||
const MCOperand &MO2 = MI->getOperand(Op+1);
|
||||
const MCOperand &MO3 = MI->getOperand(Op+2);
|
||||
|
||||
O << "[" << getRegisterName(MO1.getReg()) << "], ";
|
||||
|
||||
if (MO2.getReg()) {
|
||||
O << (char)ARM_AM::getAM3Op(MO3.getImm())
|
||||
<< getRegisterName(MO2.getReg());
|
||||
return;
|
||||
}
|
||||
|
||||
unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
|
||||
O << '#'
|
||||
<< ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
|
||||
<< ImmOffs;
|
||||
}
|
||||
|
||||
void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
|
||||
raw_ostream &O) {
|
||||
const MCOperand &MO1 = MI->getOperand(Op);
|
||||
const MCOperand &MO2 = MI->getOperand(Op+1);
|
||||
const MCOperand &MO3 = MI->getOperand(Op+2);
|
||||
|
||||
O << '[' << getRegisterName(MO1.getReg());
|
||||
|
||||
@ -297,6 +325,18 @@ void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
|
||||
O << ']';
|
||||
}
|
||||
|
||||
void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
|
||||
raw_ostream &O) {
|
||||
const MCOperand &MO3 = MI->getOperand(Op+2);
|
||||
unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
|
||||
|
||||
if (IdxMode == ARMII::IndexModePost) {
|
||||
printAM3PostIndexOp(MI, Op, O);
|
||||
return;
|
||||
}
|
||||
printAM3PreOrOffsetIndexOp(MI, Op, O);
|
||||
}
|
||||
|
||||
void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
|
||||
unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
|
||||
@ -49,9 +49,14 @@ public:
|
||||
raw_ostream &O);
|
||||
void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O);
|
||||
|
||||
void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printAM3PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O);
|
||||
void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O);
|
||||
|
||||
void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
|
||||
18
test/MC/ARM/arm_addrmode3.s
Normal file
18
test/MC/ARM/arm_addrmode3.s
Normal file
@ -0,0 +1,18 @@
|
||||
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s
|
||||
|
||||
@ CHECK: ldrsbt r1, [r0], +r2 @ encoding: [0xd2,0x10,0xb0,0xe0]
|
||||
@ CHECK: ldrsbt r1, [r0], #4 @ encoding: [0xd4,0x10,0xf0,0xe0]
|
||||
@ CHECK: ldrsht r1, [r0], +r2 @ encoding: [0xf2,0x10,0xb0,0xe0]
|
||||
@ CHECK: ldrsht r1, [r0], #4 @ encoding: [0xf4,0x10,0xf0,0xe0]
|
||||
@ CHECK: ldrht r1, [r0], +r2 @ encoding: [0xb2,0x10,0xb0,0xe0]
|
||||
@ CHECK: ldrht r1, [r0], #4 @ encoding: [0xb4,0x10,0xf0,0xe0]
|
||||
@ CHECK: strht r1, [r0], +r2 @ encoding: [0xb2,0x10,0xa0,0xe0]
|
||||
@ CHECK: strht r1, [r0], #4 @ encoding: [0xb4,0x10,0xe0,0xe0]
|
||||
ldrsbt r1, [r0], r2
|
||||
ldrsbt r1, [r0], #4
|
||||
ldrsht r1, [r0], r2
|
||||
ldrsht r1, [r0], #4
|
||||
ldrht r1, [r0], r2
|
||||
ldrht r1, [r0], #4
|
||||
strht r1, [r0], r2
|
||||
strht r1, [r0], #4
|
||||
Loading…
x
Reference in New Issue
Block a user