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AMDGPU: Change fdiv lowering based on !fpmath metadata
If 2.5 ulp is acceptable, denormals are not required, and isn't a reciprocal which will already be handled, replace with a faster fdiv. Simplify the lowering tests by using per function subtarget features. llvm-svn: 276051
This commit is contained in:
Matt Arsenault
parent
7e559dbd5a
commit
75622c9e16
@ -20,6 +20,7 @@ class AMDGPUInstrPrinter;
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class AMDGPUSubtarget;
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class AMDGPUTargetMachine;
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class FunctionPass;
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class GCNTargetMachine;
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struct MachineSchedContext;
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class MCAsmInfo;
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class raw_ostream;
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@ -50,7 +51,7 @@ FunctionPass *createSIFixSGPRCopiesPass();
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FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
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FunctionPass *createSIDebuggerInsertNopsPass();
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FunctionPass *createSIInsertWaitsPass();
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FunctionPass *createAMDGPUCodeGenPreparePass(const TargetMachine *TM = nullptr);
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FunctionPass *createAMDGPUCodeGenPreparePass(const GCNTargetMachine *TM = nullptr);
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ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C);
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@ -14,7 +14,9 @@
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUIntrinsicInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "AMDGPUTargetMachine.h"
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#include "llvm/Analysis/DivergenceAnalysis.h"
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#include "llvm/CodeGen/Passes.h"
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@ -30,15 +32,28 @@ using namespace llvm;
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namespace {
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class AMDGPUCodeGenPrepare : public FunctionPass,
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public InstVisitor<AMDGPUCodeGenPrepare> {
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public InstVisitor<AMDGPUCodeGenPrepare, bool> {
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const GCNTargetMachine *TM;
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const SISubtarget *ST;
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DivergenceAnalysis *DA;
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const TargetMachine *TM;
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Module *Mod;
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bool HasUnsafeFPMath;
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public:
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static char ID;
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AMDGPUCodeGenPrepare(const TargetMachine *TM = nullptr) :
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FunctionPass(ID),
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TM(TM) { }
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TM(static_cast<const GCNTargetMachine *>(TM)),
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ST(nullptr),
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DA(nullptr),
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Mod(nullptr),
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HasUnsafeFPMath(false) { }
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bool visitFDiv(BinaryOperator &I);
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bool visitInstruction(Instruction &I) {
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return false;
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}
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bool doInitialization(Module &M) override;
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bool runOnFunction(Function &F) override;
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@ -55,7 +70,92 @@ public:
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} // End anonymous namespace
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static bool shouldKeepFDivF32(Value *Num, bool UnsafeDiv) {
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const ConstantFP *CNum = dyn_cast<ConstantFP>(Num);
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if (!CNum)
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return false;
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// Reciprocal f32 is handled separately without denormals.
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return UnsafeDiv && CNum->isExactlyValue(+1.0);
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}
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// Insert an intrinsic for fast fdiv for safe math situations where we can
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// reduce precision. Leave fdiv for situations where the generic node is
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// expected to be optimized.
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bool AMDGPUCodeGenPrepare::visitFDiv(BinaryOperator &FDiv) {
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Type *Ty = FDiv.getType();
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// TODO: Handle half
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if (!Ty->getScalarType()->isFloatTy())
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return false;
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MDNode *FPMath = FDiv.getMetadata(LLVMContext::MD_fpmath);
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if (!FPMath)
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return false;
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const FPMathOperator *FPOp = cast<const FPMathOperator>(&FDiv);
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float ULP = FPOp->getFPAccuracy();
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if (ULP < 2.5f)
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return false;
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FastMathFlags FMF = FPOp->getFastMathFlags();
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bool UnsafeDiv = HasUnsafeFPMath || FMF.unsafeAlgebra() ||
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FMF.allowReciprocal();
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if (ST->hasFP32Denormals() && !UnsafeDiv)
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return false;
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IRBuilder<> Builder(FDiv.getParent(), std::next(FDiv.getIterator()), FPMath);
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Builder.setFastMathFlags(FMF);
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Builder.SetCurrentDebugLocation(FDiv.getDebugLoc());
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const AMDGPUIntrinsicInfo *II = TM->getIntrinsicInfo();
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Function *Decl
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= II->getDeclaration(Mod, AMDGPUIntrinsic::amdgcn_fdiv_fast, {});
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Value *Num = FDiv.getOperand(0);
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Value *Den = FDiv.getOperand(1);
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Value *NewFDiv = nullptr;
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if (VectorType *VT = dyn_cast<VectorType>(Ty)) {
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NewFDiv = UndefValue::get(VT);
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// FIXME: Doesn't do the right thing for cases where the vector is partially
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// constant. This works when the scalarizer pass is run first.
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for (unsigned I = 0, E = VT->getNumElements(); I != E; ++I) {
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Value *NumEltI = Builder.CreateExtractElement(Num, I);
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Value *DenEltI = Builder.CreateExtractElement(Den, I);
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Value *NewElt;
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if (shouldKeepFDivF32(NumEltI, UnsafeDiv)) {
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NewElt = Builder.CreateFDiv(NumEltI, DenEltI);
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} else {
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NewElt = Builder.CreateCall(Decl, { NumEltI, DenEltI });
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}
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NewFDiv = Builder.CreateInsertElement(NewFDiv, NewElt, I);
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}
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} else {
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if (!shouldKeepFDivF32(Num, UnsafeDiv))
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NewFDiv = Builder.CreateCall(Decl, { Num, Den });
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}
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if (NewFDiv) {
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FDiv.replaceAllUsesWith(NewFDiv);
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NewFDiv->takeName(&FDiv);
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FDiv.eraseFromParent();
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}
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return true;
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}
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static bool hasUnsafeFPMath(const Function &F) {
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Attribute Attr = F.getFnAttribute("unsafe-fp-math");
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return Attr.getValueAsString() == "true";
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}
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bool AMDGPUCodeGenPrepare::doInitialization(Module &M) {
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Mod = &M;
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return false;
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}
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@ -63,10 +163,21 @@ bool AMDGPUCodeGenPrepare::runOnFunction(Function &F) {
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if (!TM || skipFunction(F))
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return false;
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ST = &TM->getSubtarget<SISubtarget>(F);
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DA = &getAnalysis<DivergenceAnalysis>();
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visit(F);
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HasUnsafeFPMath = hasUnsafeFPMath(F);
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return true;
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bool MadeChange = false;
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for (BasicBlock &BB : F) {
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BasicBlock::iterator Next;
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for (BasicBlock::iterator I = BB.begin(), E = BB.end(); I != E; I = Next) {
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Next = std::next(I);
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MadeChange |= visit(*I);
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}
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}
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return MadeChange;
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}
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INITIALIZE_TM_PASS_BEGIN(AMDGPUCodeGenPrepare, DEBUG_TYPE,
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@ -77,6 +188,6 @@ INITIALIZE_TM_PASS_END(AMDGPUCodeGenPrepare, DEBUG_TYPE,
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char AMDGPUCodeGenPrepare::ID = 0;
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FunctionPass *llvm::createAMDGPUCodeGenPreparePass(const TargetMachine *TM) {
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FunctionPass *llvm::createAMDGPUCodeGenPreparePass(const GCNTargetMachine *TM) {
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return new AMDGPUCodeGenPrepare(TM);
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}
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@ -29,16 +29,39 @@ static const char *const IntrinsicNameTable[] = {
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#undef GET_INTRINSIC_NAME_TABLE
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};
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std::string AMDGPUIntrinsicInfo::getName(unsigned IntrID, Type **Tys,
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unsigned numTys) const {
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if (IntrID < Intrinsic::num_intrinsics) {
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return nullptr;
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}
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namespace {
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#define GET_INTRINSIC_ATTRIBUTES
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#include "AMDGPUGenIntrinsics.inc"
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#undef GET_INTRINSIC_ATTRIBUTES
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}
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StringRef AMDGPUIntrinsicInfo::getName(unsigned IntrID,
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ArrayRef<Type *> Tys) const {
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if (IntrID < Intrinsic::num_intrinsics)
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return StringRef();
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assert(IntrID < AMDGPUIntrinsic::num_AMDGPU_intrinsics &&
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"Invalid intrinsic ID");
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std::string Result(IntrinsicNameTable[IntrID - Intrinsic::num_intrinsics]);
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return Result;
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return IntrinsicNameTable[IntrID - Intrinsic::num_intrinsics];
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}
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std::string AMDGPUIntrinsicInfo::getName(unsigned IntrID, Type **Tys,
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unsigned NumTys) const {
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return getName(IntrID, makeArrayRef(Tys, NumTys)).str();
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}
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FunctionType *AMDGPUIntrinsicInfo::getType(LLVMContext &Context, unsigned ID,
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ArrayRef<Type*> Tys) const {
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// FIXME: Re-use Intrinsic::getType machinery
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switch (ID) {
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case AMDGPUIntrinsic::amdgcn_fdiv_fast: {
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Type *F32Ty = Type::getFloatTy(Context);
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return FunctionType::get(F32Ty, { F32Ty, F32Ty }, false);
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}
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default:
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llvm_unreachable("unhandled intrinsic");
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}
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}
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unsigned AMDGPUIntrinsicInfo::lookupName(const char *NameData,
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@ -69,7 +92,19 @@ bool AMDGPUIntrinsicInfo::isOverloaded(unsigned id) const {
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}
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Function *AMDGPUIntrinsicInfo::getDeclaration(Module *M, unsigned IntrID,
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Type **Tys,
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unsigned numTys) const {
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llvm_unreachable("Not implemented");
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ArrayRef<Type *> Tys) const {
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FunctionType *FTy = getType(M->getContext(), IntrID, Tys);
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Function *F
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= cast<Function>(M->getOrInsertFunction(getName(IntrID, Tys), FTy));
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AttributeSet AS = getAttributes(M->getContext(),
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static_cast<AMDGPUIntrinsic::ID>(IntrID));
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F->setAttributes(AS);
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return F;
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}
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Function *AMDGPUIntrinsicInfo::getDeclaration(Module *M, unsigned IntrID,
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Type **Tys,
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unsigned NumTys) const {
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return getDeclaration(M, IntrID, makeArrayRef(Tys, NumTys));
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}
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@ -34,13 +34,23 @@ enum ID {
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class AMDGPUIntrinsicInfo final : public TargetIntrinsicInfo {
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public:
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AMDGPUIntrinsicInfo();
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StringRef getName(unsigned IntrId, ArrayRef<Type *> Tys = None) const;
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std::string getName(unsigned IntrId, Type **Tys = nullptr,
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unsigned numTys = 0) const override;
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unsigned NumTys = 0) const override;
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unsigned lookupName(const char *Name, unsigned Len) const override;
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bool isOverloaded(unsigned IID) const override;
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Function *getDeclaration(Module *M, unsigned ID,
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Type **Tys = nullptr,
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unsigned numTys = 0) const override;
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unsigned NumTys = 0) const override;
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Function *getDeclaration(Module *M, unsigned ID,
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ArrayRef<Type *> = None) const;
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FunctionType *getType(LLVMContext &Context, unsigned ID,
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ArrayRef<Type*> Tys = None) const;
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};
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} // end namespace llvm
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@ -309,6 +309,7 @@ public:
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ScheduleDAGInstrs *
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createMachineScheduler(MachineSchedContext *C) const override;
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void addIRPasses() override;
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bool addPreISel() override;
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void addMachineSSAOptimization() override;
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bool addInstSelector() override;
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@ -499,6 +500,13 @@ void GCNPassConfig::addMachineSSAOptimization() {
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addPass(&DeadMachineInstructionElimID);
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}
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void GCNPassConfig::addIRPasses() {
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// TODO: May want to move later or split into an early and late one.
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addPass(createAMDGPUCodeGenPreparePass(&getGCNTargetMachine()));
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AMDGPUPassConfig::addIRPasses();
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}
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bool GCNPassConfig::addInstSelector() {
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AMDGPUPassConfig::addInstSelector();
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addPass(createSILowerI1CopiesPass());
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@ -2113,6 +2113,9 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
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Op->getVTList(), Ops, VT, MMO);
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}
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case AMDGPUIntrinsic::amdgcn_fdiv_fast: {
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return lowerFDIV_FAST(Op, DAG);
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}
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case AMDGPUIntrinsic::SI_vs_load_input:
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return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
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Op.getOperand(1),
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@ -2427,7 +2430,8 @@ SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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// Catch division cases where we can use shortcuts with rcp and rsq
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// instructions.
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SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
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SDValue SITargetLowering::lowerFastUnsafeFDIV(SDValue Op,
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SelectionDAG &DAG) const {
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SDLoc SL(Op);
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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@ -2468,47 +2472,48 @@ SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
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return SDValue();
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}
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// Faster 2.5 ULP division that does not support denormals.
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SDValue SITargetLowering::lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const {
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SDLoc SL(Op);
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SDValue LHS = Op.getOperand(1);
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SDValue RHS = Op.getOperand(2);
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SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
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const APFloat K0Val(BitsToFloat(0x6f800000));
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const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32);
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const APFloat K1Val(BitsToFloat(0x2f800000));
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const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32);
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const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
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EVT SetCCVT =
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getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
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SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
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SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
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// TODO: Should this propagate fast-math-flags?
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r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
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// rcp does not support denormals.
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SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
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SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
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return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
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}
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SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
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if (SDValue FastLowered = LowerFastFDIV(Op, DAG))
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if (SDValue FastLowered = lowerFastUnsafeFDIV(Op, DAG))
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return FastLowered;
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SDLoc SL(Op);
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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// faster 2.5 ulp fdiv when using -amdgpu-fast-fdiv flag
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if (EnableAMDGPUFastFDIV) {
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// This does not support denormals.
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SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
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const APFloat K0Val(BitsToFloat(0x6f800000));
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const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32);
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const APFloat K1Val(BitsToFloat(0x2f800000));
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const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32);
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const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
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EVT SetCCVT =
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getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
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SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
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SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
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// TODO: Should this propagate fast-math-flags?
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r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
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// rcp does not support denormals.
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SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
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SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
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return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
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}
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// Generates more precise fpdiv32.
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const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
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SDVTList ScaleVT = DAG.getVTList(MVT::f32, MVT::i1);
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@ -2538,7 +2543,7 @@ SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
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SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
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if (DAG.getTarget().Options.UnsafeFPMath)
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return LowerFastFDIV(Op, DAG);
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return lowerFastUnsafeFDIV(Op, DAG);
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SDLoc SL(Op);
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SDValue X = Op.getOperand(0);
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@ -36,7 +36,8 @@ class SITargetLowering final : public AMDGPUTargetLowering {
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SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
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@ -7,7 +7,8 @@
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//
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//===----------------------------------------------------------------------===//
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//
|
||||
// SI Intrinsic Definitions
|
||||
// Backend internal SI Intrinsic Definitions. User code should not
|
||||
// directly use these.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -177,6 +178,12 @@ let TargetPrefix = "SI", isTarget = 1 in {
|
||||
} // End TargetPrefix = "SI", isTarget = 1
|
||||
|
||||
let TargetPrefix = "amdgcn", isTarget = 1 in {
|
||||
// Emit 2.5 ulp, no denormal division. Should only be inserted by
|
||||
// pass based on !fpmath metadata.
|
||||
def int_amdgcn_fdiv_fast : Intrinsic<
|
||||
[llvm_float_ty], [llvm_float_ty], [IntrNoMem]
|
||||
>;
|
||||
|
||||
/* Control flow Intrinsics */
|
||||
|
||||
def int_amdgcn_if : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_empty_ty], []>;
|
||||
|
||||
@ -1,8 +1,242 @@
|
||||
; RUN: opt -S -mtriple=amdgcn-- -amdgpu-codegenprepare < %s | FileCheck %s
|
||||
; RUN: opt -S -amdgpu-codegenprepare < %s
|
||||
; RUN: opt -S -mtriple=amdgcn-- -amdgpu-codegenprepare %s | FileCheck %s
|
||||
; RUN: opt -S -amdgpu-codegenprepare %s | FileCheck -check-prefix=NOOP %s
|
||||
; Make sure this doesn't crash with no triple
|
||||
|
||||
; CHECK-LABEL: @foo(
|
||||
define void @foo() {
|
||||
; NOOP-LABEL: @noop_fdiv_fpmath(
|
||||
; NOOP: %md.25ulp = fdiv float %a, %b, !fpmath !0
|
||||
define void @noop_fdiv_fpmath(float addrspace(1)* %out, float %a, float %b) #3 {
|
||||
%md.25ulp = fdiv float %a, %b, !fpmath !0
|
||||
store volatile float %md.25ulp, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @fdiv_fpmath(
|
||||
; CHECK: %no.md = fdiv float %a, %b{{$}}
|
||||
; CHECK: %md.half.ulp = fdiv float %a, %b, !fpmath !1
|
||||
; CHECK: %md.1ulp = fdiv float %a, %b, !fpmath !2
|
||||
; CHECK: %md.25ulp = call float @llvm.amdgcn.fdiv.fast(float %a, float %b), !fpmath !0
|
||||
; CHECK: %md.3ulp = call float @llvm.amdgcn.fdiv.fast(float %a, float %b), !fpmath !3
|
||||
; CHECK: %fast.md.25ulp = call fast float @llvm.amdgcn.fdiv.fast(float %a, float %b), !fpmath !0
|
||||
; CHECK: arcp.md.25ulp = call arcp float @llvm.amdgcn.fdiv.fast(float %a, float %b), !fpmath !0
|
||||
define void @fdiv_fpmath(float addrspace(1)* %out, float %a, float %b) #1 {
|
||||
%no.md = fdiv float %a, %b
|
||||
store volatile float %no.md, float addrspace(1)* %out
|
||||
|
||||
%md.half.ulp = fdiv float %a, %b, !fpmath !1
|
||||
store volatile float %md.half.ulp, float addrspace(1)* %out
|
||||
|
||||
%md.1ulp = fdiv float %a, %b, !fpmath !2
|
||||
store volatile float %md.1ulp, float addrspace(1)* %out
|
||||
|
||||
%md.25ulp = fdiv float %a, %b, !fpmath !0
|
||||
store volatile float %md.25ulp, float addrspace(1)* %out
|
||||
|
||||
%md.3ulp = fdiv float %a, %b, !fpmath !3
|
||||
store volatile float %md.3ulp, float addrspace(1)* %out
|
||||
|
||||
%fast.md.25ulp = fdiv fast float %a, %b, !fpmath !0
|
||||
store volatile float %fast.md.25ulp, float addrspace(1)* %out
|
||||
|
||||
%arcp.md.25ulp = fdiv arcp float %a, %b, !fpmath !0
|
||||
store volatile float %arcp.md.25ulp, float addrspace(1)* %out
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @rcp_fdiv_fpmath(
|
||||
; CHECK: %no.md = fdiv float 1.000000e+00, %x{{$}}
|
||||
; CHECK: %md.half.ulp = fdiv float 1.000000e+00, %x, !fpmath !1
|
||||
; CHECK: %arcp.no.md = fdiv arcp float 1.000000e+00, %x{{$}}
|
||||
; CHECK: %arcp.25ulp = fdiv arcp float 1.000000e+00, %x, !fpmath !0
|
||||
; CHECK: %fast.no.md = fdiv fast float 1.000000e+00, %x{{$}}
|
||||
; CHECK: %fast.25ulp = fdiv fast float 1.000000e+00, %x, !fpmath !0
|
||||
define void @rcp_fdiv_fpmath(float addrspace(1)* %out, float %x) #1 {
|
||||
%no.md = fdiv float 1.0, %x
|
||||
store volatile float %no.md, float addrspace(1)* %out
|
||||
|
||||
%md.half.ulp = fdiv float 1.0, %x, !fpmath !1
|
||||
store volatile float %md.half.ulp, float addrspace(1)* %out
|
||||
|
||||
%arcp.no.md = fdiv arcp float 1.0, %x
|
||||
store volatile float %arcp.no.md, float addrspace(1)* %out
|
||||
|
||||
%arcp.25ulp = fdiv arcp float 1.0, %x, !fpmath !0
|
||||
store volatile float %arcp.25ulp, float addrspace(1)* %out
|
||||
|
||||
%fast.no.md = fdiv fast float 1.0, %x
|
||||
store volatile float %fast.no.md, float addrspace(1)* %out
|
||||
|
||||
%fast.25ulp = fdiv fast float 1.0, %x, !fpmath !0
|
||||
store volatile float %fast.25ulp, float addrspace(1)* %out
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @fdiv_fpmath_vector(
|
||||
; CHECK: %no.md = fdiv <2 x float> %a, %b{{$}}
|
||||
; CHECK: %md.half.ulp = fdiv <2 x float> %a, %b, !fpmath !1
|
||||
; CHECK: %md.1ulp = fdiv <2 x float> %a, %b, !fpmath !2
|
||||
|
||||
; CHECK: %[[A0:[0-9]+]] = extractelement <2 x float> %a, i64 0
|
||||
; CHECK: %[[B0:[0-9]+]] = extractelement <2 x float> %b, i64 0
|
||||
; CHECK: %[[FDIV0:[0-9]+]] = call float @llvm.amdgcn.fdiv.fast(float %[[A0]], float %[[B0]]), !fpmath !0
|
||||
; CHECK: %[[INS0:[0-9]+]] = insertelement <2 x float> undef, float %[[FDIV0]], i64 0
|
||||
; CHECK: %[[A1:[0-9]+]] = extractelement <2 x float> %a, i64 1
|
||||
; CHECK: %[[B1:[0-9]+]] = extractelement <2 x float> %b, i64 1
|
||||
; CHECK: %[[FDIV1:[0-9]+]] = call float @llvm.amdgcn.fdiv.fast(float %[[A1]], float %[[B1]]), !fpmath !0
|
||||
; CHECK: %md.25ulp = insertelement <2 x float> %[[INS0]], float %[[FDIV1]], i64 1
|
||||
define void @fdiv_fpmath_vector(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) #1 {
|
||||
%no.md = fdiv <2 x float> %a, %b
|
||||
store volatile <2 x float> %no.md, <2 x float> addrspace(1)* %out
|
||||
|
||||
%md.half.ulp = fdiv <2 x float> %a, %b, !fpmath !1
|
||||
store volatile <2 x float> %md.half.ulp, <2 x float> addrspace(1)* %out
|
||||
|
||||
%md.1ulp = fdiv <2 x float> %a, %b, !fpmath !2
|
||||
store volatile <2 x float> %md.1ulp, <2 x float> addrspace(1)* %out
|
||||
|
||||
%md.25ulp = fdiv <2 x float> %a, %b, !fpmath !0
|
||||
store volatile <2 x float> %md.25ulp, <2 x float> addrspace(1)* %out
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @rcp_fdiv_fpmath_vector(
|
||||
; CHECK: %no.md = fdiv <2 x float> <float 1.000000e+00, float 1.000000e+00>, %x{{$}}
|
||||
; CHECK: %md.half.ulp = fdiv <2 x float> <float 1.000000e+00, float 1.000000e+00>, %x, !fpmath !1
|
||||
; CHECK: %arcp.no.md = fdiv arcp <2 x float> <float 1.000000e+00, float 1.000000e+00>, %x{{$}}
|
||||
; CHECK: %fast.no.md = fdiv fast <2 x float> <float 1.000000e+00, float 1.000000e+00>, %x{{$}}
|
||||
|
||||
; CHECK: extractelement <2 x float> %x
|
||||
; CHECK: fdiv arcp float 1.000000e+00, %{{[0-9]+}}, !fpmath !0
|
||||
; CHECK: extractelement <2 x float> %x
|
||||
; CHECK: fdiv arcp float 1.000000e+00, %{{[0-9]+}}, !fpmath !0
|
||||
; CHECK: store volatile <2 x float> %arcp.25ulp
|
||||
|
||||
; CHECK: fdiv fast float 1.000000e+00, %{{[0-9]+}}, !fpmath !0
|
||||
; CHECK: fdiv fast float 1.000000e+00, %{{[0-9]+}}, !fpmath !0
|
||||
; CHECK: store volatile <2 x float> %fast.25ulp, <2 x float> addrspace(1)* %out
|
||||
define void @rcp_fdiv_fpmath_vector(<2 x float> addrspace(1)* %out, <2 x float> %x) #1 {
|
||||
%no.md = fdiv <2 x float> <float 1.0, float 1.0>, %x
|
||||
store volatile <2 x float> %no.md, <2 x float> addrspace(1)* %out
|
||||
|
||||
%md.half.ulp = fdiv <2 x float> <float 1.0, float 1.0>, %x, !fpmath !1
|
||||
store volatile <2 x float> %md.half.ulp, <2 x float> addrspace(1)* %out
|
||||
|
||||
%arcp.no.md = fdiv arcp <2 x float> <float 1.0, float 1.0>, %x
|
||||
store volatile <2 x float> %arcp.no.md, <2 x float> addrspace(1)* %out
|
||||
|
||||
%fast.no.md = fdiv fast <2 x float> <float 1.0, float 1.0>, %x
|
||||
store volatile <2 x float> %fast.no.md, <2 x float> addrspace(1)* %out
|
||||
|
||||
%arcp.25ulp = fdiv arcp <2 x float> <float 1.0, float 1.0>, %x, !fpmath !0
|
||||
store volatile <2 x float> %arcp.25ulp, <2 x float> addrspace(1)* %out
|
||||
|
||||
%fast.25ulp = fdiv fast <2 x float> <float 1.0, float 1.0>, %x, !fpmath !0
|
||||
store volatile <2 x float> %fast.25ulp, <2 x float> addrspace(1)* %out
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @rcp_fdiv_fpmath_vector_nonsplat(
|
||||
; CHECK: %no.md = fdiv <2 x float> <float 1.000000e+00, float 2.000000e+00>, %x
|
||||
; CHECK: %arcp.no.md = fdiv arcp <2 x float> <float 1.000000e+00, float 2.000000e+00>, %x
|
||||
; CHECK: %fast.no.md = fdiv fast <2 x float> <float 1.000000e+00, float 2.000000e+00>, %x{{$}}
|
||||
|
||||
; CHECK: %[[X0:[0-9]+]] = extractelement <2 x float> %x, i64 0
|
||||
; CHECK: fdiv arcp float 1.000000e+00, %[[X0]], !fpmath !0
|
||||
; CHECK: %[[X1:[0-9]+]] = extractelement <2 x float> %x, i64 1
|
||||
; CHECK: call arcp float @llvm.amdgcn.fdiv.fast(float 2.000000e+00, float %[[X1]]), !fpmath !0
|
||||
; CHECK: store volatile <2 x float> %arcp.25ulp
|
||||
|
||||
; CHECK: %[[X0:[0-9]+]] = extractelement <2 x float> %x, i64 0
|
||||
; CHECK: fdiv fast float 1.000000e+00, %[[X0]], !fpmath !0
|
||||
; CHECK: %[[X1:[0-9]+]] = extractelement <2 x float> %x, i64 1
|
||||
; CHECK: call fast float @llvm.amdgcn.fdiv.fast(float 2.000000e+00, float %[[X1]]), !fpmath !0
|
||||
; CHECK: store volatile <2 x float> %fast.25ulp
|
||||
define void @rcp_fdiv_fpmath_vector_nonsplat(<2 x float> addrspace(1)* %out, <2 x float> %x) #1 {
|
||||
%no.md = fdiv <2 x float> <float 1.0, float 2.0>, %x
|
||||
store volatile <2 x float> %no.md, <2 x float> addrspace(1)* %out
|
||||
|
||||
%arcp.no.md = fdiv arcp <2 x float> <float 1.0, float 2.0>, %x
|
||||
store volatile <2 x float> %arcp.no.md, <2 x float> addrspace(1)* %out
|
||||
|
||||
%fast.no.md = fdiv fast <2 x float> <float 1.0, float 2.0>, %x
|
||||
store volatile <2 x float> %fast.no.md, <2 x float> addrspace(1)* %out
|
||||
|
||||
%arcp.25ulp = fdiv arcp <2 x float> <float 1.0, float 2.0>, %x, !fpmath !0
|
||||
store volatile <2 x float> %arcp.25ulp, <2 x float> addrspace(1)* %out
|
||||
|
||||
%fast.25ulp = fdiv fast <2 x float> <float 1.0, float 2.0>, %x, !fpmath !0
|
||||
store volatile <2 x float> %fast.25ulp, <2 x float> addrspace(1)* %out
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; FIXME: Should be able to get fdiv for 1.0 component
|
||||
; CHECK-LABEL: @rcp_fdiv_fpmath_vector_partial_constant(
|
||||
; CHECK: call arcp float @llvm.amdgcn.fdiv.fast(float %{{[0-9]+}}, float %{{[0-9]+}}), !fpmath !0
|
||||
; CHECK: call arcp float @llvm.amdgcn.fdiv.fast(float %{{[0-9]+}}, float %{{[0-9]+}}), !fpmath !0
|
||||
; CHECK: store volatile <2 x float> %arcp.25ulp
|
||||
|
||||
; CHECK: call fast float @llvm.amdgcn.fdiv.fast(float %{{[0-9]+}}, float %{{[0-9]+}}), !fpmath !0
|
||||
; CHECK: call fast float @llvm.amdgcn.fdiv.fast(float %{{[0-9]+}}, float %{{[0-9]+}}), !fpmath !0
|
||||
; CHECK: store volatile <2 x float> %fast.25ulp
|
||||
define void @rcp_fdiv_fpmath_vector_partial_constant(<2 x float> addrspace(1)* %out, <2 x float> %x, <2 x float> %y) #1 {
|
||||
%x.insert = insertelement <2 x float> %x, float 1.0, i32 0
|
||||
|
||||
%arcp.25ulp = fdiv arcp <2 x float> %x.insert, %y, !fpmath !0
|
||||
store volatile <2 x float> %arcp.25ulp, <2 x float> addrspace(1)* %out
|
||||
|
||||
%fast.25ulp = fdiv fast <2 x float> %x.insert, %y, !fpmath !0
|
||||
store volatile <2 x float> %fast.25ulp, <2 x float> addrspace(1)* %out
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @fdiv_fpmath_f32_denormals(
|
||||
; CHECK: %no.md = fdiv float %a, %b{{$}}
|
||||
; CHECK: %md.half.ulp = fdiv float %a, %b, !fpmath !1
|
||||
; CHECK: %md.1ulp = fdiv float %a, %b, !fpmath !2
|
||||
; CHECK: %md.25ulp = fdiv float %a, %b, !fpmath !0
|
||||
; CHECK: %md.3ulp = fdiv float %a, %b, !fpmath !3
|
||||
; CHECK: call fast float @llvm.amdgcn.fdiv.fast(float %a, float %b), !fpmath !0
|
||||
; CHECK: call arcp float @llvm.amdgcn.fdiv.fast(float %a, float %b), !fpmath !0
|
||||
define void @fdiv_fpmath_f32_denormals(float addrspace(1)* %out, float %a, float %b) #2 {
|
||||
%no.md = fdiv float %a, %b
|
||||
store volatile float %no.md, float addrspace(1)* %out
|
||||
|
||||
%md.half.ulp = fdiv float %a, %b, !fpmath !1
|
||||
store volatile float %md.half.ulp, float addrspace(1)* %out
|
||||
|
||||
%md.1ulp = fdiv float %a, %b, !fpmath !2
|
||||
store volatile float %md.1ulp, float addrspace(1)* %out
|
||||
|
||||
%md.25ulp = fdiv float %a, %b, !fpmath !0
|
||||
store volatile float %md.25ulp, float addrspace(1)* %out
|
||||
|
||||
%md.3ulp = fdiv float %a, %b, !fpmath !3
|
||||
store volatile float %md.3ulp, float addrspace(1)* %out
|
||||
|
||||
%fast.md.25ulp = fdiv fast float %a, %b, !fpmath !0
|
||||
store volatile float %fast.md.25ulp, float addrspace(1)* %out
|
||||
|
||||
%arcp.md.25ulp = fdiv arcp float %a, %b, !fpmath !0
|
||||
store volatile float %arcp.md.25ulp, float addrspace(1)* %out
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind optnone noinline }
|
||||
attributes #1 = { nounwind }
|
||||
attributes #2 = { nounwind "target-features"="+fp32-denormals" }
|
||||
|
||||
; CHECK: !0 = !{float 2.500000e+00}
|
||||
; CHECK: !1 = !{float 5.000000e-01}
|
||||
; CHECK: !2 = !{float 1.000000e+00}
|
||||
; CHECK: !3 = !{float 3.000000e+00}
|
||||
|
||||
!0 = !{float 2.500000e+00}
|
||||
!1 = !{float 5.000000e-01}
|
||||
!2 = !{float 1.000000e+00}
|
||||
!3 = !{float 3.000000e+00}
|
||||
|
||||
@ -1,8 +1,4 @@
|
||||
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
|
||||
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=I754 -check-prefix=FUNC %s
|
||||
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -amdgpu-fast-fdiv < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
|
||||
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=I754 -check-prefix=FUNC %s
|
||||
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=UNSAFE-FP -check-prefix=FUNC %s
|
||||
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
|
||||
|
||||
; These tests check that fdiv is expanded correctly and also test that the
|
||||
@ -15,22 +11,59 @@
|
||||
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
|
||||
|
||||
; UNSAFE-FP: v_rcp_f32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; SI: v_div_scale_f32
|
||||
; SI-DAG: v_div_scale_f32
|
||||
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
|
||||
; I754-DAG: v_div_scale_f32
|
||||
; I754-DAG: v_rcp_f32
|
||||
; I754-DAG: v_fma_f32
|
||||
; I754-DAG: v_mul_f32
|
||||
; I754-DAG: v_fma_f32
|
||||
; I754-DAG: v_div_fixup_f32
|
||||
define void @fdiv_f32(float addrspace(1)* %out, float %a, float %b) {
|
||||
; SI: v_fma_f32
|
||||
; SI: v_fma_f32
|
||||
; SI: v_mul_f32
|
||||
; SI: v_fma_f32
|
||||
; SI: v_fma_f32
|
||||
; SI: v_fma_f32
|
||||
; SI: v_div_fmas_f32
|
||||
; SI: v_div_fixup_f32
|
||||
define void @fdiv_f32(float addrspace(1)* %out, float %a, float %b) #0 {
|
||||
entry:
|
||||
%0 = fdiv float %a, %b
|
||||
store float %0, float addrspace(1)* %out
|
||||
%fdiv = fdiv float %a, %b
|
||||
store float %fdiv, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}fdiv_25ulp_f32:
|
||||
; SI: v_cndmask_b32
|
||||
; SI: v_mul_f32
|
||||
; SI: v_rcp_f32
|
||||
; SI: v_mul_f32
|
||||
; SI: v_mul_f32
|
||||
define void @fdiv_25ulp_f32(float addrspace(1)* %out, float %a, float %b) #0 {
|
||||
entry:
|
||||
%fdiv = fdiv float %a, %b, !fpmath !0
|
||||
store float %fdiv, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; Use correct fdiv
|
||||
; FUNC-LABEL: {{^}}fdiv_25ulp_denormals_f32:
|
||||
; SI: v_fma_f32
|
||||
; SI: v_div_fmas_f32
|
||||
; SI: v_div_fixup_f32
|
||||
define void @fdiv_25ulp_denormals_f32(float addrspace(1)* %out, float %a, float %b) #2 {
|
||||
entry:
|
||||
%fdiv = fdiv float %a, %b, !fpmath !0
|
||||
store float %fdiv, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}fdiv_fast_denormals_f32:
|
||||
; SI: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
|
||||
; SI: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
|
||||
; SI-NOT: [[RESULT]]
|
||||
; SI: buffer_store_dword [[RESULT]]
|
||||
define void @fdiv_fast_denormals_f32(float addrspace(1)* %out, float %a, float %b) #2 {
|
||||
entry:
|
||||
%fdiv = fdiv fast float %a, %b
|
||||
store float %fdiv, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -38,15 +71,14 @@ entry:
|
||||
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
|
||||
|
||||
; UNSAFE-FP: v_rcp_f32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
define void @fdiv_f32_fast_math(float addrspace(1)* %out, float %a, float %b) {
|
||||
; SI: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
|
||||
; SI: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
|
||||
; SI-NOT: [[RESULT]]
|
||||
; SI: buffer_store_dword [[RESULT]]
|
||||
define void @fdiv_f32_fast_math(float addrspace(1)* %out, float %a, float %b) #0 {
|
||||
entry:
|
||||
%0 = fdiv fast float %a, %b
|
||||
store float %0, float addrspace(1)* %out
|
||||
%fdiv = fdiv fast float %a, %b
|
||||
store float %fdiv, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -54,15 +86,14 @@ entry:
|
||||
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
|
||||
|
||||
; UNSAFE-FP: v_rcp_f32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
define void @fdiv_f32_arcp_math(float addrspace(1)* %out, float %a, float %b) {
|
||||
; SI: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
|
||||
; SI: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
|
||||
; SI-NOT: [[RESULT]]
|
||||
; SI: buffer_store_dword [[RESULT]]
|
||||
define void @fdiv_f32_arcp_math(float addrspace(1)* %out, float %a, float %b) #0 {
|
||||
entry:
|
||||
%0 = fdiv arcp float %a, %b
|
||||
store float %0, float addrspace(1)* %out
|
||||
%fdiv = fdiv arcp float %a, %b
|
||||
store float %fdiv, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -72,26 +103,24 @@ entry:
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
|
||||
|
||||
; UNSAFE-FP: v_rcp_f32
|
||||
; UNSAFE-FP: v_rcp_f32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_fixup_f32
|
||||
; I754: v_div_fixup_f32
|
||||
define void @fdiv_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
|
||||
; SI: v_div_scale_f32
|
||||
; SI: v_div_scale_f32
|
||||
; SI: v_div_scale_f32
|
||||
; SI: v_div_scale_f32
|
||||
define void @fdiv_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) #0 {
|
||||
entry:
|
||||
%0 = fdiv <2 x float> %a, %b
|
||||
store <2 x float> %0, <2 x float> addrspace(1)* %out
|
||||
%fdiv = fdiv <2 x float> %a, %b
|
||||
store <2 x float> %fdiv, <2 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}fdiv_ulp25_v2f32:
|
||||
; SI: v_cmp_gt_f32
|
||||
; SI: v_cmp_gt_f32
|
||||
define void @fdiv_ulp25_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) #0 {
|
||||
entry:
|
||||
%fdiv = fdiv arcp <2 x float> %a, %b, !fpmath !0
|
||||
store <2 x float> %fdiv, <2 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -101,19 +130,12 @@ entry:
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
|
||||
|
||||
; UNSAFE-FP: v_rcp_f32
|
||||
; UNSAFE-FP: v_rcp_f32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
define void @fdiv_v2f32_fast_math(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
|
||||
; SI: v_rcp_f32
|
||||
; SI: v_rcp_f32
|
||||
define void @fdiv_v2f32_fast_math(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) #0 {
|
||||
entry:
|
||||
%0 = fdiv fast <2 x float> %a, %b
|
||||
store <2 x float> %0, <2 x float> addrspace(1)* %out
|
||||
%fdiv = fdiv fast <2 x float> %a, %b
|
||||
store <2 x float> %fdiv, <2 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -123,19 +145,12 @@ entry:
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
|
||||
|
||||
; UNSAFE-FP: v_rcp_f32
|
||||
; UNSAFE-FP: v_rcp_f32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
define void @fdiv_v2f32_arcp_math(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
|
||||
; SI: v_rcp_f32
|
||||
; SI: v_rcp_f32
|
||||
define void @fdiv_v2f32_arcp_math(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) #0 {
|
||||
entry:
|
||||
%0 = fdiv arcp <2 x float> %a, %b
|
||||
store <2 x float> %0, <2 x float> addrspace(1)* %out
|
||||
%fdiv = fdiv arcp <2 x float> %a, %b
|
||||
store <2 x float> %fdiv, <2 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -149,37 +164,11 @@ entry:
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
||||
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_scale_f32
|
||||
; I754: v_div_fixup_f32
|
||||
; I754: v_div_fixup_f32
|
||||
; I754: v_div_fixup_f32
|
||||
; I754: v_div_fixup_f32
|
||||
define void @fdiv_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
|
||||
; SI: v_div_fixup_f32
|
||||
; SI: v_div_fixup_f32
|
||||
; SI: v_div_fixup_f32
|
||||
; SI: v_div_fixup_f32
|
||||
define void @fdiv_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) #0 {
|
||||
%b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
|
||||
%a = load <4 x float>, <4 x float> addrspace(1) * %in
|
||||
%b = load <4 x float>, <4 x float> addrspace(1) * %b_ptr
|
||||
@ -198,24 +187,11 @@ define void @fdiv_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
||||
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
define void @fdiv_v4f32_fast_math(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
|
||||
; SI: v_rcp_f32
|
||||
; SI: v_rcp_f32
|
||||
; SI: v_rcp_f32
|
||||
; SI: v_rcp_f32
|
||||
define void @fdiv_v4f32_fast_math(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) #0 {
|
||||
%b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
|
||||
%a = load <4 x float>, <4 x float> addrspace(1) * %in
|
||||
%b = load <4 x float>, <4 x float> addrspace(1) * %b_ptr
|
||||
@ -234,24 +210,11 @@ define void @fdiv_v4f32_fast_math(<4 x float> addrspace(1)* %out, <4 x float> ad
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
||||
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
||||
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_rcp_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
; UNSAFE-FP: v_mul_f32_e32
|
||||
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
; SI-DAG: v_rcp_f32
|
||||
; SI-DAG: v_mul_f32
|
||||
define void @fdiv_v4f32_arcp_math(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
|
||||
; SI: v_rcp_f32
|
||||
; SI: v_rcp_f32
|
||||
; SI: v_rcp_f32
|
||||
; SI: v_rcp_f32
|
||||
define void @fdiv_v4f32_arcp_math(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) #0 {
|
||||
%b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
|
||||
%a = load <4 x float>, <4 x float> addrspace(1) * %in
|
||||
%b = load <4 x float>, <4 x float> addrspace(1) * %b_ptr
|
||||
@ -259,3 +222,9 @@ define void @fdiv_v4f32_arcp_math(<4 x float> addrspace(1)* %out, <4 x float> ad
|
||||
store <4 x float> %result, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind "enable-unsafe-fp-math"="false" "target-features"="-fp32-denormals" }
|
||||
attributes #1 = { nounwind "enable-unsafe-fp-math"="true" "target-features"="-fp32-denormals" }
|
||||
attributes #2 = { nounwind "enable-unsafe-fp-math"="false" "target-features"="+fp32-denormals" }
|
||||
|
||||
!0 = !{float 2.500000e+00}
|
||||
|
||||
18
test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll
Normal file
18
test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll
Normal file
@ -0,0 +1,18 @@
|
||||
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
declare float @llvm.amdgcn.fdiv.fast(float, float) #0
|
||||
|
||||
; CHECK-LABEL: {{^}}test_fdiv_fast:
|
||||
; CHECK: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc
|
||||
; CHECK: v_mul_f32_e32
|
||||
; CHECK: v_rcp_f32_e32
|
||||
; CHECK: v_mul_f32_e32
|
||||
; CHECK: v_mul_f32_e32
|
||||
define void @test_fdiv_fast(float addrspace(1)* %out, float %a, float %b) #1 {
|
||||
%fdiv = call float @llvm.amdgcn.fdiv.fast(float %a, float %b)
|
||||
store float %fdiv, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind readnone }
|
||||
attributes #1 = { nounwind }
|
||||
Loading…
Reference in New Issue
Block a user