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[X86][MS-compatability]Allow named synonymous for MS-assembly operators

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This patch enhances X86AsmParser's immediate expression parsing abilities, to include a named synonymous for selected binary/unary bitwise operators: {and,shl,shr,or,xor,not}, ultimately achieving better MS-compatability
MASM reference:
https://msdn.microsoft.com/en-us/library/94b6khh4.aspx

Differential Revision: D31277

llvm-svn: 299439
This commit is contained in:
Coby Tayree 2017-04-04 14:43:23 +00:00
parent 981bbb8176
commit 75e681a367
2 changed files with 68 additions and 7 deletions
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27
lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -717,6 +717,7 @@ private:
std::unique_ptr<X86Operand>
ParseIntelSegmentOverride(unsigned SegReg, SMLoc Start, unsigned Size);
std::unique_ptr<X86Operand> ParseRoundingModeOp(SMLoc Start, SMLoc End);
bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM);
bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
std::unique_ptr<X86Operand>
ParseIntelBracExpression(unsigned SegReg, SMLoc Start, int64_t ImmDisp,
@ -1298,6 +1299,30 @@ RewriteIntelBracExpression(SmallVectorImpl<AsmRewrite> &AsmRewrites,
}
}
// Some binary bitwise operators have a named synonymous
// Query a candidate string for being such a named operator
// and if so - invoke the appropriate handler
bool X86AsmParser::ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM) {
// A named operator should be either lower or upper case, but not a mix
if (Name.compare(Name.lower()) && Name.compare(Name.upper()))
return false;
if (Name.equals_lower("not"))
SM.onNot();
else if (Name.equals_lower("or"))
SM.onOr();
else if (Name.equals_lower("shl"))
SM.onLShift();
else if (Name.equals_lower("shr"))
SM.onRShift();
else if (Name.equals_lower("xor"))
SM.onXor();
else if (Name.equals_lower("and"))
SM.onAnd();
else
return false;
return true;
}
bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
MCAsmParser &Parser = getParser();
const AsmToken &Tok = Parser.getTok();
@ -1339,6 +1364,8 @@ bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
UpdateLocLex = false;
if (TK != AsmToken::String && !ParseRegister(TmpReg, IdentLoc, End)) {
SM.onRegister(TmpReg);
} else if (ParseIntelNamedOperator(Identifier, SM)) {
UpdateLocLex = true;
} else if (!isParsingInlineAsm()) {
if (getParser().parsePrimaryExpr(Val, End))
return Error(Tok.getLoc(), "Unexpected identifier!");

48
test/MC/X86/intel-syntax-bitwise-ops.s
View File

@ -6,19 +6,53 @@
and ecx, 1+2
// CHECK: andl $3, %ecx
and ecx, 1|2
// CHECK: andl $3, %ecx
// CHECK: andl $3, %ecx
and ecx, 1 or 2
// CHECK: andl $3, %ecx
and ecx, 1 OR 2
// CHECK: andl $3, %ecx
and ecx, 1*3
// CHECK: andl $1, %ecx
and ecx, 1&3
// CHECK: andl $0, %ecx
// CHECK: andl $1, %ecx
and ecx, 1 and 3
// CHECK: andl $1, %ecx
and ecx, 1 AND 3
// CHECK: andl $0, %ecx
and ecx, (1&2)
// CHECK: andl $3, %ecx
// CHECK: andl $0, %ecx
and ecx, (1 and 2)
// CHECK: andl $0, %ecx
and ecx, (1 AND 2)
// CHECK: andl $3, %ecx
and ecx, ((1)|2)
// CHECK: andl $1, %ecx
// CHECK: andl $3, %ecx
and ecx, ((1) or 2)
// CHECK: andl $3, %ecx
and ecx, ((1) OR 2)
// CHECK: andl $1, %ecx
and ecx, 1&2+3
// CHECK: addl $4938, %eax
// CHECK: andl $1, %ecx
and ecx, 1 and 2+3
// CHECK: andl $1, %ecx
and ecx, 1 AND 2+3
// CHECK: addl $4938, %eax
add eax, 9876 >> 1
// CHECK: addl $19752, %eax
// CHECK: addl $4938, %eax
add eax, 9876 shr 1
// CHECK: addl $4938, %eax
add eax, 9876 SHR 1
// CHECK: addl $19752, %eax
add eax, 9876 << 1
// CHECK: addl $5, %eax
// CHECK: addl $19752, %eax
add eax, 9876 shl 1
// CHECK: addl $19752, %eax
add eax, 9876 SHL 1
// CHECK: addl $5, %eax
add eax, 6 ^ 3
// CHECK: addl $5, %eax
add eax, 6 xor 3
// CHECK: addl $5, %eax
add eax, 6 XOR 3
// CHECK: addl $5, %eax
add eax, 6 XOR 3 shl 1 SHR 1