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Allow strict subclasses of register classes, this way we can handle
ARM instructions with: foo GPR, rGPR which happens a lot. llvm-svn: 112025
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@ -112,9 +112,10 @@ struct OperandsSignature {
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if (!RC)
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return false;
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// For now, all the operands must have the same register class.
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// For now, all the operands must have the same register class or be
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// a strict subclass of the destination.
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if (DstRC) {
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if (DstRC != RC)
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if (DstRC != RC && !DstRC->hasSubClass(RC))
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return false;
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} else
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DstRC = RC;
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