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[PowerPC] Remove redundant direct moves when extracting integers and converting to FP
This patch corresponds to review: https://reviews.llvm.org/D21354 We use direct moves for extracting integer elements from vectors. We also use direct moves when converting integers to FP. When these operations are chained, we get a direct move out of a VSR followed by a direct move back into a VSR. These are redundant - all we need to do is line up the element and convert. llvm-svn: 275796
This commit is contained in:
Nemanja Ivanovic
parent
43bf7a6963
commit
7649511189
@ -1029,6 +1029,28 @@ def : Pat<(int_ppc_vsx_xvrsqrtesp v4f32:$A),
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def : Pat<(int_ppc_vsx_xvrsqrtedp v2f64:$A),
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(XVRSQRTEDP $A)>;
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let Predicates = [IsLittleEndian] in {
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def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
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(f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
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def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
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(f64 (XSCVSXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>;
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def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
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(f64 (XSCVUXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
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def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
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(f64 (XSCVUXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>;
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} // IsLittleEndian
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let Predicates = [IsBigEndian] in {
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def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
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(f64 (XSCVSXDDP (COPY_TO_REGCLASS $S, VSFRC)))>;
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def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
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(f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
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def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
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(f64 (XSCVUXDDP (COPY_TO_REGCLASS $S, VSFRC)))>;
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def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
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(f64 (XSCVUXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
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} // IsBigEndian
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} // AddedComplexity
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} // HasVSX
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@ -1235,6 +1257,27 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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def XSCVSPDPN : XX2Form<60, 331, (outs vssrc:$XT), (ins vsrc:$XB),
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"xscvspdpn $XT, $XB", IIC_VecFP, []>;
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let Predicates = [IsLittleEndian] in {
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def : Pat<(f32 (PPCfcfids (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
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(f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
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def : Pat<(f32 (PPCfcfids (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
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(f32 (XSCVSXDSP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>;
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def : Pat<(f32 (PPCfcfidus (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
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(f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
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def : Pat<(f32 (PPCfcfidus (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
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(f32 (XSCVUXDSP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>;
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}
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let Predicates = [IsBigEndian] in {
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def : Pat<(f32 (PPCfcfids (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
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(f32 (XSCVSXDSP (COPY_TO_REGCLASS $S, VSFRC)))>;
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def : Pat<(f32 (PPCfcfids (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
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(f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
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def : Pat<(f32 (PPCfcfidus (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
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(f32 (XSCVUXDSP (COPY_TO_REGCLASS $S, VSFRC)))>;
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def : Pat<(f32 (PPCfcfidus (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
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(f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
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}
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} // AddedComplexity = 400
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} // HasP8Vector
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107
test/CodeGen/PowerPC/remove-redundant-moves.ll
Normal file
107
test/CodeGen/PowerPC/remove-redundant-moves.ll
Normal file
@ -0,0 +1,107 @@
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; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE
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define double @test1(<2 x i64> %a) {
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entry:
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; CHECK-LABEL: test1
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; CHECK: xxswapd [[SW:[0-9]+]], 34
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; CHECK: xscvsxddp 1, [[SW]]
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; CHECK-BE-LABEL: test1
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; CHECK-BE: xxlor [[CP:[0-9]+]], 34, 34
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; CHECK-BE: xscvsxddp 1, [[CP]]
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%0 = extractelement <2 x i64> %a, i32 0
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%1 = sitofp i64 %0 to double
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ret double %1
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}
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define double @test2(<2 x i64> %a) {
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entry:
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; CHECK-LABEL: test2
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; CHECK: xxlor [[CP:[0-9]+]], 34, 34
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; CHECK: xscvsxddp 1, [[CP]]
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; CHECK-BE-LABEL: test2
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; CHECK-BE: xxswapd [[SW:[0-9]+]], 34
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; CHECK-BE: xscvsxddp 1, [[SW]]
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%0 = extractelement <2 x i64> %a, i32 1
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%1 = sitofp i64 %0 to double
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ret double %1
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}
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define float @test1f(<2 x i64> %a) {
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entry:
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; CHECK-LABEL: test1f
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; CHECK: xxswapd [[SW:[0-9]+]], 34
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; CHECK: xscvsxdsp 1, [[SW]]
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; CHECK-BE-LABEL: test1f
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; CHECK-BE: xxlor [[CP:[0-9]+]], 34, 34
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; CHECK-BE: xscvsxdsp 1, [[CP]]
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%0 = extractelement <2 x i64> %a, i32 0
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%1 = sitofp i64 %0 to float
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ret float %1
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}
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define float @test2f(<2 x i64> %a) {
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entry:
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; CHECK-LABEL: test2f
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; CHECK: xxlor [[CP:[0-9]+]], 34, 34
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; CHECK: xscvsxdsp 1, [[CP]]
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; CHECK-BE-LABEL: test2f
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; CHECK-BE: xxswapd [[SW:[0-9]+]], 34
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; CHECK-BE: xscvsxdsp 1, [[SW]]
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%0 = extractelement <2 x i64> %a, i32 1
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%1 = sitofp i64 %0 to float
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ret float %1
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}
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define double @test1u(<2 x i64> %a) {
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entry:
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; CHECK-LABEL: test1u
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; CHECK: xxswapd [[SW:[0-9]+]], 34
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; CHECK: xscvuxddp 1, [[SW]]
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; CHECK-BE-LABEL: test1u
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; CHECK-BE: xxlor [[CP:[0-9]+]], 34, 34
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; CHECK-BE: xscvuxddp 1, [[CP]]
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%0 = extractelement <2 x i64> %a, i32 0
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%1 = uitofp i64 %0 to double
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ret double %1
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}
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define double @test2u(<2 x i64> %a) {
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entry:
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; CHECK-LABEL: test2u
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; CHECK: xxlor [[CP:[0-9]+]], 34, 34
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; CHECK: xscvuxddp 1, [[CP]]
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; CHECK-BE-LABEL: test2u
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; CHECK-BE: xxswapd [[SW:[0-9]+]], 34
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; CHECK-BE: xscvuxddp 1, [[SW]]
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%0 = extractelement <2 x i64> %a, i32 1
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%1 = uitofp i64 %0 to double
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ret double %1
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}
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define float @test1fu(<2 x i64> %a) {
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entry:
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; CHECK-LABEL: test1fu
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; CHECK: xxswapd [[SW:[0-9]+]], 34
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; CHECK: xscvuxdsp 1, [[SW]]
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; CHECK-BE-LABEL: test1fu
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; CHECK-BE: xxlor [[CP:[0-9]+]], 34, 34
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; CHECK-BE: xscvuxdsp 1, [[CP]]
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%0 = extractelement <2 x i64> %a, i32 0
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%1 = uitofp i64 %0 to float
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ret float %1
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}
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define float @test2fu(<2 x i64> %a) {
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entry:
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; CHECK-LABEL: test2fu
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; CHECK: xxlor [[CP:[0-9]+]], 34, 34
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; CHECK: xscvuxdsp 1, [[CP]]
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; CHECK-BE-LABEL: test2fu
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; CHECK-BE: xxswapd [[SW:[0-9]+]], 34
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; CHECK-BE: xscvuxdsp 1, [[SW]]
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%0 = extractelement <2 x i64> %a, i32 1
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%1 = uitofp i64 %0 to float
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ret float %1
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}
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